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Searched refs:MC_SEQ_WR_CTL_D1_LP (Results 1 - 12 of 12) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
btcd.h	`154 #define MC_SEQ_WR_CTL_D1_LP 0x2a80`
nid.h	`812 #define MC_SEQ_WR_CTL_D1_LP 0x2a80`
cikd.h	`705 #define MC_SEQ_WR_CTL_D1_LP 0x2a80`
sid.h	`580 #define MC_SEQ_WR_CTL_D1_LP 0x2a80`
radeon_btc_dpm.c	`1887 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 2042 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`
evergreend.h	`330 #define MC_SEQ_WR_CTL_D1_LP 0x2a80`
radeon_cypress_dpm.c	`1005 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;`
radeon_ni_dpm.c	`2799 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 2895 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`
radeon_ci_dpm.c	`4458 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 4656 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`
radeon_si_dpm.c	`5456 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5556 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sid.h	`582 #define MC_SEQ_WR_CTL_D1_LP 0xAA0`
amdgpu_si_dpm.c	`5912 *out_reg = MC_SEQ_WR_CTL_D1_LP; 6012 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));`

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