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  /src/sys/arch/mips/mips/
mips32_subr.S 4 #undef MIPS3
mips32r2_subr.S 4 #undef MIPS3
mips64_subr.S 4 #undef MIPS3
mips64r2_subr.S 4 #undef MIPS3
cache.c 115 #if defined(MIPS3) || defined(MIPS4)
120 #endif /* MIPS3 || MIPS4 */
122 #if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
130 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS64 + MIPS32R2 + MIPS64R2) > 0
195 #if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
243 #if defined(MIPS1) || defined(MIPS3) || defined(MIPS4)
253 #if defined(MIPS3) || defined(MIPS4)
384 #if defined(MIPS3) || defined(MIPS4)
653 #endif /* MIPS3 || MIPS4 */
667 #if (MIPS2 + MIPS3 + MIPS4) >
    [all...]
mipsX_subr.S 133 #if defined(MIPS3)
173 #if (MIPS3 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) != 1
187 #if (MIPS3 + MIPS64 + MIPS64R2) > 0
243 #if defined(MIPS3)
244 .set mips3 define
270 #elif defined(MIPS3)
502 #ifdef MIPS3
507 #if (MIPS3 + MIPS64 + MIPS64R2) > 0
819 #ifdef MIPS3
835 #ifdef MIPS3
    [all...]
mips_stacktrace.c 86 #ifdef MIPS3
147 #if defined(MIPS3) /* r4000 family (mips-III CPU) */
153 #endif /* MIPS3 */
  /src/sys/arch/sgimips/sgimips/
clock.c 98 #if defined(MIPS3)
105 #endif /* MIPS3 */
112 #if defined(MIPS3)
124 #endif /* MIPS3 */
machdep.c 151 #if defined(MIPS3)
166 #endif /* defined(MIPS3) */
176 #if defined(MIPS3)
355 * Note ci_cycles_per_hz is for mips3_clockintr.c for MIPS3 so
561 #if defined(MIPS3)
580 #endif /* MIPS3 */
944 #if defined(MIPS3)
  /src/sys/arch/mips/include/
cache.h 236 (MIPS3 + MIPS4) == 0 \
245 (MIPS3 + MIPS4) == 0 \
locore.h 59 #define MIPS3 1
69 #if (MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0
70 #error at least one of MIPS1, MIPS3, MIPS4, MIPS32, MIPS32R2, MIPS64, or MIPS64R2 must be specified
73 /* Shortcut for MIPS3 or above defined */
74 #if defined(MIPS3) || defined(MIPS4) \
82 #if !defined(MIPS3) && !defined(MIPS4)
170 #if ((MIPS1 + MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 1) || defined(_LOCORE)
190 #elif defined(MIPS3) || defined(MIPS4)
cpuregs.h 126 /* Map virtual address to index in mips3 r4k virtually-indexed cache */
156 # if (MIPS1 + MIPS3 + MIPS32 + MIPS64) == 0
166 #elif MIPS3 > 0
336 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
357 * The bits in the MIPS3 config register.
484 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
829 * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
834 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 && MIPS1 != 0
840 #if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) != 0 && MIPS1 == 0
  /src/sys/arch/hpcmips/conf/
std.hpcmips.vr41 5 options MIPS3 # R4000/R4400/R4600 CPUs
LROUTER 14 options MIPS3 # R4000/R4400/R4600 CPUs
17 makeoptions CPUFLAGS="-mips3" # CPU codegen options
  /src/sys/arch/pmax/pmax/
bus.c 91 #ifdef MIPS3
203 #ifdef MIPS3
342 #endif /* MIPS3 */
dec_maxine.c 384 #if defined(MIPS3)
402 #if defined(MIPS3)
dec_3maxplus.c 437 #if defined(MIPS3)
455 #if defined(MIPS3)
bus_dma.c 85 #ifdef MIPS3
516 #ifdef MIPS3
655 #endif /* MIPS3 */
dec_3min.c 457 #if defined(MIPS3)
  /src/sys/arch/newsmips/newsmips/
locore_machdep.S 81 #ifdef MIPS3
82 .set mips3 define
131 #endif /* MIPS3 */
bus.c 82 #ifdef MIPS3
561 #ifdef MIPS3
700 #endif /* MIPS3 */
  /src/sys/arch/sgimips/dev/
int.c 77 #ifdef MIPS3
208 #ifdef MIPS3
454 #ifdef MIPS3
527 #endif /* MIPS3 */
  /src/sys/arch/emips/emips/
bus_dma.c 85 #ifdef MIPS3
516 #ifdef MIPS3
655 #endif /* MIPS3 */
  /src/lib/libc_fp/arch/mips/
fpdf.S 42 #ifdef MIPS3
fpsf.S 42 #ifdef MIPS3

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