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    Searched refs:MIPS_PHYS_TO_KSEG1 (Results 1 - 25 of 157) sorted by relevancy

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  /src/sys/arch/playstation2/ee/
gifreg.h 32 #define GIF_CTRL_REG MIPS_PHYS_TO_KSEG1(0x10003000)
intcreg.h 32 #define I_STAT_REG MIPS_PHYS_TO_KSEG1(0x1000f000)
33 #define I_MASK_REG MIPS_PHYS_TO_KSEG1(0x1000f010)
timerreg.h 47 #define T_COUNT_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + TIMER_OFS * (x)))
48 #define T_MODE_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \
50 #define T_COMP_REG(x) MIPS_PHYS_TO_KSEG1((TIMER_REGBASE + \
58 #define T0_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000000)
59 #define T0_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000010)
60 #define T0_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000020)
61 #define T0_HOLD_REG MIPS_PHYS_TO_KSEG1(0x10000030)
62 #define T1_COUNT_REG MIPS_PHYS_TO_KSEG1(0x10000800)
63 #define T1_MODE_REG MIPS_PHYS_TO_KSEG1(0x10000810)
64 #define T1_COMP_REG MIPS_PHYS_TO_KSEG1(0x10000820
    [all...]
gsreg.h 32 #define GS_S_PMODE_REG MIPS_PHYS_TO_KSEG1(0x12000000)
33 #define GS_S_SMODE1_REG MIPS_PHYS_TO_KSEG1(0x12000010)
34 #define GS_S_SMODE2_REG MIPS_PHYS_TO_KSEG1(0x12000020)
35 #define GS_S_SRFSH_REG MIPS_PHYS_TO_KSEG1(0x12000030)
36 #define GS_S_SYNCH1_REG MIPS_PHYS_TO_KSEG1(0x12000040)
37 #define GS_S_SYNCH2_REG MIPS_PHYS_TO_KSEG1(0x12000050)
38 #define GS_S_SYNCV_REG MIPS_PHYS_TO_KSEG1(0x12000060)
39 #define GS_S_DISPFB1_REG MIPS_PHYS_TO_KSEG1(0x12000070)
40 #define GS_S_DISPLAY1_REG MIPS_PHYS_TO_KSEG1(0x12000080)
41 #define GS_S_DISPFB2_REG MIPS_PHYS_TO_KSEG1(0x12000090
    [all...]
dmacreg.h 41 #define DMAC_REGBASE MIPS_PHYS_TO_KSEG1(0x10008000)
47 #define D_CTRL_REG MIPS_PHYS_TO_KSEG1(0x1000e000) /* DMA control */
48 #define D_STAT_REG MIPS_PHYS_TO_KSEG1(0x1000e010) /* interrupt status */
49 #define D_PCR_REG MIPS_PHYS_TO_KSEG1(0x1000e020) /* priority control */
50 #define D_SQWC_REG MIPS_PHYS_TO_KSEG1(0x1000e030) /* interleave size */
51 #define D_RBOR_REG MIPS_PHYS_TO_KSEG1(0x1000e040) /* ring buffer addr */
52 #define D_RBSR_REG MIPS_PHYS_TO_KSEG1(0x1000e050) /* ring buffer size */
53 #define D_STADR_REG MIPS_PHYS_TO_KSEG1(0x1000e060) /* stall address */
54 #define D_ENABLER_REG MIPS_PHYS_TO_KSEG1(0x1000f520) /* DMA enable (r) */
55 #define D_ENABLEW_REG MIPS_PHYS_TO_KSEG1(0x1000f590) /* DMA enable (w) *
    [all...]
  /src/sys/arch/playstation2/dev/
sbusreg.h 32 #define SBUS_SMFLG_REG MIPS_PHYS_TO_KSEG1(0x1000f230)
36 #define SBUS_AIF_INTSR_REG16 MIPS_PHYS_TO_KSEG1(0x18000004)
37 #define SBUS_AIF_INTEN_REG16 MIPS_PHYS_TO_KSEG1(0x18000006)
39 #define SBUS_PCMCIA_EXC1_REG16 MIPS_PHYS_TO_KSEG1(0x1f801476)
40 #define SBUS_PCMCIA_CSC1_REG16 MIPS_PHYS_TO_KSEG1(0x1f801464)
41 #define SBUS_PCMCIA_IMR1_REG16 MIPS_PHYS_TO_KSEG1(0x1f801468)
42 #define SBUS_PCMCIA_TIMR_REG16 MIPS_PHYS_TO_KSEG1(0x1f80147e)
43 #define SBUS_PCMCIA3_TIMR_REG16 MIPS_PHYS_TO_KSEG1(0x1f801466)
spdreg.h 37 #define SPD_INTR_ENABLE_REG16 MIPS_PHYS_TO_KSEG1(0x1400002a)
38 #define SPD_INTR_STATUS_REG16 MIPS_PHYS_TO_KSEG1(0x14000028)
39 #define SPD_INTR_CLEAR_REG16 MIPS_PHYS_TO_KSEG1(0x14000128)
48 #define SPD_IO_DIR_REG8 MIPS_PHYS_TO_KSEG1(0x1400002c)
49 #define SPD_IO_DATA_REG8 MIPS_PHYS_TO_KSEG1(0x1400002e)
59 #define SPD_XFR_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000032)
60 #define SPD_HDD_IO_BASE MIPS_PHYS_TO_KSEG1(0x14000040)
61 #define SPD_IF_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14000064)
if_smapreg.h 51 #define SMAP_TXFIFO_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14001000)
52 #define SMAP_TXFIFO_PTR_REG16 MIPS_PHYS_TO_KSEG1(0x14001004)
53 #define SMAP_TXFIFO_FRAME_REG8 MIPS_PHYS_TO_KSEG1(0x1400100c)
54 #define SMAP_TXFIFO_FRAME_INC_REG8 MIPS_PHYS_TO_KSEG1(0x14001010)
55 #define SMAP_TXFIFO_DATA_REG MIPS_PHYS_TO_KSEG1(0x14001100)
56 #define SMAP_RXFIFO_CTRL_REG8 MIPS_PHYS_TO_KSEG1(0x14001030)
57 #define SMAP_RXFIFO_PTR_REG16 MIPS_PHYS_TO_KSEG1(0x14001034)
58 #define SMAP_RXFIFO_FRAME_REG8 MIPS_PHYS_TO_KSEG1(0x1400103c)
59 #define SMAP_RXFIFO_FRAME_DEC_REG8 MIPS_PHYS_TO_KSEG1(0x14001040)
60 #define SMAP_RXFIFO_DATA_REG MIPS_PHYS_TO_KSEG1(0x14001200
    [all...]
  /src/sys/arch/sgimips/stand/common/
iris_autoconf.c 40 wd33c93_init((void *)MIPS_PHYS_TO_KSEG1(SCSIA_ADDR),
41 (void *)MIPS_PHYS_TO_KSEG1(SCSID_ADDR));
  /src/sys/arch/sgimips/sgimips/
arcemu.h 65 (MIPS_PHYS_TO_KSEG1((_x)) >= 0xa0000000 && \
66 MIPS_PHYS_TO_KSEG1((_x)) < 0xa0800000)
89 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) |= 0x10;
91 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) &= ~0x10;
99 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) |= 0x20;
101 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) &= ~0x20;
109 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) |= 0x40;
111 *(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f8e0000) &= ~0x40;
119 if (*(volatile uint8_t *)MIPS_PHYS_TO_KSEG1(0x1f800001) & 0x01)
128 *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(0x1f880002) |= 0x0100
    [all...]
  /src/sys/arch/evbmips/malta/
leds.c 50 uint8_t *ledbar = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_LEDBAR);
58 uint32_t *ledbar = (uint32_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCIIWORD);
66 uint8_t *leds = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCII_BASE);
79 uint8_t *leds = (uint8_t *)MIPS_PHYS_TO_KSEG1(MALTA_ASCII_BASE);
  /src/sys/arch/pmax/pmax/
memc_3min.c 70 siz = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MSR);
71 mer = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_MER);
72 adr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_AER);
75 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KMIN_REG_TIMEOUT) = 0;
dec_3max.c 141 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
147 mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK), MIPS_INT_MASK_1);
153 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
155 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
172 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_ERRADR) = 0;
175 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CHKSYN) = 0;
239 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) &
242 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
262 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
272 "r"(MIPS_PHYS_TO_KSEG1(KN02_SYS_CLOCK)))
    [all...]
dec_5100.c 100 mc_cpuspeed(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK), MIPS_INT_MASK_2);
114 icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR);
116 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR) = icsr;
168 icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR);
175 "r"(MIPS_PHYS_TO_KSEG1(KN01_SYS_CLOCK)));
214 icsr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR);
216 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN230_SYS_ICSR) = icsr;
  /src/sys/arch/mips/sibyte/dev/
sbbuswatch.c 51 (void)READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
52 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
53 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
76 MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
82 MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS));
84 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
87 MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS));
89 WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
  /src/sys/arch/cobalt/stand/boot/
pci.c 45 pcicfg_addr = (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_PCICFG_ADDR);
46 pcicfg_data = (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_PCICFG_DATA);
clock.c 71 mcclock_reg = (void *)MIPS_PHYS_TO_KSEG1(MCCLOCK_BASE + MCCLOCK_REG);
72 mcclock_data = (void *)MIPS_PHYS_TO_KSEG1(MCCLOCK_BASE + MCCLOCK_DATA);
pciide.c 57 cmdreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
59 ctlreg = MIPS_PHYS_TO_KSEG1(COBALT_IO_SPACE_BASE +
  /src/sys/arch/pmax/include/
tc_machdep.h 63 #include <mips/cpuregs.h> /* defines MIPS_PHYS_TO_KSEG1 */
76 #define TC_PHYS_TO_UNCACHED(addr) MIPS_PHYS_TO_KSEG1(addr)
85 #define KV(x) ((tc_addr_t)MIPS_PHYS_TO_KSEG1(x))
  /src/sys/arch/mips/atheros/
ar5312_board.c 94 ptr = (const uint8_t *) MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END - 0x1000);
124 MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END-0x1000);
132 if (end == (uint8_t *) MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END)) {
136 MIPS_PHYS_TO_KSEG1(AR5312_FLASH_END-0x1000 + 0xf8);
ar_console.c 84 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1(platformsw->apsw_uart0_base);
96 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1(platformsw->apsw_uart0_base);
108 (volatile uint32_t *)MIPS_PHYS_TO_KSEG1(platformsw->apsw_uart0_base);
  /src/sys/arch/algor/algor/
led.c 58 #define LEDBASE MIPS_PHYS_TO_KSEG1(P4032_LED)
61 #define LEDBASE MIPS_PHYS_TO_KSEG1(P5064_LED1)
67 #define LEDBASE MIPS_PHYS_TO_KSEG1(P6032_HDSP2532_BASE + HD2532_CRAM)
  /src/sys/arch/evbmips/alchemy/
dbau1500.c 48 (*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)))
50 (*((volatile uint16_t *)MIPS_PHYS_TO_KSEG1(x)) = (v))
90 whoami = *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(DBAU1500_WHOAMI));
  /src/sys/arch/hpcmips/stand/lcboot/
extern.h 84 (__REG_1(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))) \
87 (__REG_2(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))) \
90 (__REG_4(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))) \
94 (__REG_1(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))))
96 (__REG_2(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))))
98 (__REG_4(MIPS_PHYS_TO_KSEG1((u_int32_t) (base) + (off))))
  /src/sys/arch/playstation2/include/
bootinfo.h 43 (*(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(BOOTINFO_BLOCK_BASE + (x)))

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