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    Searched refs:MTK_M4U_ID (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/gpl2/dts/dist/include/dt-bindings/memory/
mt8192-larb-port.h 31 #define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0)
32 #define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_ID(0, 1)
33 #define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 2)
34 #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 3)
35 #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 4)
36 #define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5)
39 #define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_ID(1, 0)
40 #define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_ID(1, 1)
41 #define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 2)
42 #define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_ID(1, 3
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mt6779-larb-port.h 28 #define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0)
29 #define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1)
30 #define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2)
31 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3)
32 #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4)
33 #define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5)
34 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
35 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7)
36 #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8)
39 #define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0
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mt8173-larb-port.h 21 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
22 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
23 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
24 #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
25 #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
26 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
27 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
28 #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
31 #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
32 #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1
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mt8183-larb-port.h 23 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
24 #define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1)
25 #define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2)
26 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
27 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
28 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
29 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
30 #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
31 #define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8)
32 #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9
    [all...]
mt2712-larb-port.h 25 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
26 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
27 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
28 #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
29 #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
30 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
31 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
32 #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7)
35 #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
36 #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1
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mt8167-larb-port.h 20 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
21 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
22 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
23 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3)
24 #define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4)
25 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5)
26 #define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6)
27 #define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7)
30 #define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0)
31 #define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1
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mtk-memory-port.h 13 #define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))

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