1 /* $NetBSD: mt6779-larb-port.h,v 1.1.1.1 2021/11/07 16:49:56 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2019 MediaTek Inc. 6 * Author: Chao Hao <chao.hao (at) mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ 10 #define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_ 11 12 #include <dt-bindings/memory/mtk-memory-port.h> 13 14 #define M4U_LARB0_ID 0 15 #define M4U_LARB1_ID 1 16 #define M4U_LARB2_ID 2 17 #define M4U_LARB3_ID 3 18 #define M4U_LARB4_ID 4 19 #define M4U_LARB5_ID 5 20 #define M4U_LARB6_ID 6 21 #define M4U_LARB7_ID 7 22 #define M4U_LARB8_ID 8 23 #define M4U_LARB9_ID 9 24 #define M4U_LARB10_ID 10 25 #define M4U_LARB11_ID 11 26 27 /* larb0 */ 28 #define M4U_PORT_DISP_POSTMASK0 MTK_M4U_ID(M4U_LARB0_ID, 0) 29 #define M4U_PORT_DISP_OVL0_HDR MTK_M4U_ID(M4U_LARB0_ID, 1) 30 #define M4U_PORT_DISP_OVL1_HDR MTK_M4U_ID(M4U_LARB0_ID, 2) 31 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 3) 32 #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4) 33 #define M4U_PORT_DISP_PVRIC0 MTK_M4U_ID(M4U_LARB0_ID, 5) 34 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6) 35 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 7) 36 #define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 8) 37 38 /* larb1 */ 39 #define M4U_PORT_DISP_OVL0_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 0) 40 #define M4U_PORT_DISP_OVL1_2L_HDR MTK_M4U_ID(M4U_LARB1_ID, 1) 41 #define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB1_ID, 2) 42 #define M4U_PORT_DISP_OVL1_2L MTK_M4U_ID(M4U_LARB1_ID, 3) 43 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 4) 44 #define M4U_PORT_MDP_PVRIC0 MTK_M4U_ID(M4U_LARB1_ID, 5) 45 #define M4U_PORT_MDP_PVRIC1 MTK_M4U_ID(M4U_LARB1_ID, 6) 46 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB1_ID, 7) 47 #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB1_ID, 8) 48 #define M4U_PORT_MDP_WROT0_R MTK_M4U_ID(M4U_LARB1_ID, 9) 49 #define M4U_PORT_MDP_WROT0_W MTK_M4U_ID(M4U_LARB1_ID, 10) 50 #define M4U_PORT_MDP_WROT1_R MTK_M4U_ID(M4U_LARB1_ID, 11) 51 #define M4U_PORT_MDP_WROT1_W MTK_M4U_ID(M4U_LARB1_ID, 12) 52 #define M4U_PORT_DISP_FAKE1 MTK_M4U_ID(M4U_LARB1_ID, 13) 53 54 /* larb2-VDEC */ 55 #define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0) 56 #define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB2_ID, 1) 57 #define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 2) 58 #define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 3) 59 #define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 4) 60 #define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 5) 61 #define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB2_ID, 6) 62 #define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 7) 63 #define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB2_ID, 8) 64 #define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 9) 65 #define M4U_PORT_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(M4U_LARB2_ID, 10) 66 #define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11) 67 68 /* larb3-VENC */ 69 #define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) 70 #define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) 71 #define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) 72 #define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) 73 #define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) 74 #define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5) 75 #define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 6) 76 #define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB3_ID, 7) 77 #define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB3_ID, 8) 78 #define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB3_ID, 9) 79 #define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 10) 80 #define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 11) 81 #define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 12) 82 #define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 13) 83 #define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB3_ID, 14) 84 #define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 15) 85 #define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 16) 86 #define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 17) 87 #define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 18) 88 89 /* larb4-dummy */ 90 91 /* larb5-IMG */ 92 #define M4U_PORT_IMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 0) 93 #define M4U_PORT_IMGBI_D1 MTK_M4U_ID(M4U_LARB5_ID, 1) 94 #define M4U_PORT_DMGI_D1 MTK_M4U_ID(M4U_LARB5_ID, 2) 95 #define M4U_PORT_DEPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 3) 96 #define M4U_PORT_LCEI_D1 MTK_M4U_ID(M4U_LARB5_ID, 4) 97 #define M4U_PORT_SMTI_D1 MTK_M4U_ID(M4U_LARB5_ID, 5) 98 #define M4U_PORT_SMTO_D2 MTK_M4U_ID(M4U_LARB5_ID, 6) 99 #define M4U_PORT_SMTO_D1 MTK_M4U_ID(M4U_LARB5_ID, 7) 100 #define M4U_PORT_CRZO_D1 MTK_M4U_ID(M4U_LARB5_ID, 8) 101 #define M4U_PORT_IMG3O_D1 MTK_M4U_ID(M4U_LARB5_ID, 9) 102 #define M4U_PORT_VIPI_D1 MTK_M4U_ID(M4U_LARB5_ID, 10) 103 #define M4U_PORT_WPE_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 11) 104 #define M4U_PORT_WPE_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 12) 105 #define M4U_PORT_WPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 13) 106 #define M4U_PORT_TIMGO_D1 MTK_M4U_ID(M4U_LARB5_ID, 14) 107 #define M4U_PORT_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 15) 108 #define M4U_PORT_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 16) 109 #define M4U_PORT_MFB_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 17) 110 #define M4U_PORT_MFB_RDMA3 MTK_M4U_ID(M4U_LARB5_ID, 18) 111 #define M4U_PORT_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 19) 112 #define M4U_PORT_RESERVE1 MTK_M4U_ID(M4U_LARB5_ID, 20) 113 #define M4U_PORT_RESERVE2 MTK_M4U_ID(M4U_LARB5_ID, 21) 114 #define M4U_PORT_RESERVE3 MTK_M4U_ID(M4U_LARB5_ID, 22) 115 #define M4U_PORT_RESERVE4 MTK_M4U_ID(M4U_LARB5_ID, 23) 116 #define M4U_PORT_RESERVE5 MTK_M4U_ID(M4U_LARB5_ID, 24) 117 #define M4U_PORT_RESERVE6 MTK_M4U_ID(M4U_LARB5_ID, 25) 118 119 /* larb6-IMG-VPU */ 120 #define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB6_ID, 0) 121 #define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB6_ID, 1) 122 #define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB6_ID, 2) 123 124 /* larb7-DVS */ 125 #define M4U_PORT_DVS_RDMA MTK_M4U_ID(M4U_LARB7_ID, 0) 126 #define M4U_PORT_DVS_WDMA MTK_M4U_ID(M4U_LARB7_ID, 1) 127 #define M4U_PORT_DVP_RDMA MTK_M4U_ID(M4U_LARB7_ID, 2) 128 #define M4U_PORT_DVP_WDMA MTK_M4U_ID(M4U_LARB7_ID, 3) 129 130 /* larb8-IPESYS */ 131 #define M4U_PORT_FDVT_RDA MTK_M4U_ID(M4U_LARB8_ID, 0) 132 #define M4U_PORT_FDVT_RDB MTK_M4U_ID(M4U_LARB8_ID, 1) 133 #define M4U_PORT_FDVT_WRA MTK_M4U_ID(M4U_LARB8_ID, 2) 134 #define M4U_PORT_FDVT_WRB MTK_M4U_ID(M4U_LARB8_ID, 3) 135 #define M4U_PORT_FE_RD0 MTK_M4U_ID(M4U_LARB8_ID, 4) 136 #define M4U_PORT_FE_RD1 MTK_M4U_ID(M4U_LARB8_ID, 5) 137 #define M4U_PORT_FE_WR0 MTK_M4U_ID(M4U_LARB8_ID, 6) 138 #define M4U_PORT_FE_WR1 MTK_M4U_ID(M4U_LARB8_ID, 7) 139 #define M4U_PORT_RSC_RDMA0 MTK_M4U_ID(M4U_LARB8_ID, 8) 140 #define M4U_PORT_RSC_WDMA MTK_M4U_ID(M4U_LARB8_ID, 9) 141 142 /* larb9-CAM */ 143 #define M4U_PORT_CAM_IMGO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 0) 144 #define M4U_PORT_CAM_RRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 1) 145 #define M4U_PORT_CAM_LSCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 2) 146 #define M4U_PORT_CAM_BPCI_R1_C MTK_M4U_ID(M4U_LARB9_ID, 3) 147 #define M4U_PORT_CAM_YUVO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 4) 148 #define M4U_PORT_CAM_UFDI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 5) 149 #define M4U_PORT_CAM_RAWI_R2_C MTK_M4U_ID(M4U_LARB9_ID, 6) 150 #define M4U_PORT_CAM_RAWI_R5_C MTK_M4U_ID(M4U_LARB9_ID, 7) 151 #define M4U_PORT_CAM_CAMSV_1 MTK_M4U_ID(M4U_LARB9_ID, 8) 152 #define M4U_PORT_CAM_CAMSV_2 MTK_M4U_ID(M4U_LARB9_ID, 9) 153 #define M4U_PORT_CAM_CAMSV_3 MTK_M4U_ID(M4U_LARB9_ID, 10) 154 #define M4U_PORT_CAM_CAMSV_4 MTK_M4U_ID(M4U_LARB9_ID, 11) 155 #define M4U_PORT_CAM_CAMSV_5 MTK_M4U_ID(M4U_LARB9_ID, 12) 156 #define M4U_PORT_CAM_CAMSV_6 MTK_M4U_ID(M4U_LARB9_ID, 13) 157 #define M4U_PORT_CAM_AAO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 14) 158 #define M4U_PORT_CAM_AFO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 15) 159 #define M4U_PORT_CAM_FLKO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 16) 160 #define M4U_PORT_CAM_LCESO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 17) 161 #define M4U_PORT_CAM_CRZO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 18) 162 #define M4U_PORT_CAM_LTMSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 19) 163 #define M4U_PORT_CAM_RSSO_R1_C MTK_M4U_ID(M4U_LARB9_ID, 20) 164 #define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB9_ID, 21) 165 #define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB9_ID, 22) 166 #define M4U_PORT_CAM_FAKE MTK_M4U_ID(M4U_LARB9_ID, 23) 167 168 /* larb10-CAM_A */ 169 #define M4U_PORT_CAM_IMGO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 0) 170 #define M4U_PORT_CAM_RRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 1) 171 #define M4U_PORT_CAM_LSCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 2) 172 #define M4U_PORT_CAM_BPCI_R1_A MTK_M4U_ID(M4U_LARB10_ID, 3) 173 #define M4U_PORT_CAM_YUVO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 4) 174 #define M4U_PORT_CAM_UFDI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 5) 175 #define M4U_PORT_CAM_RAWI_R2_A MTK_M4U_ID(M4U_LARB10_ID, 6) 176 #define M4U_PORT_CAM_RAWI_R5_A MTK_M4U_ID(M4U_LARB10_ID, 7) 177 #define M4U_PORT_CAM_IMGO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 8) 178 #define M4U_PORT_CAM_RRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 9) 179 #define M4U_PORT_CAM_LSCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 10) 180 #define M4U_PORT_CAM_BPCI_R1_B MTK_M4U_ID(M4U_LARB10_ID, 11) 181 #define M4U_PORT_CAM_YUVO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 12) 182 #define M4U_PORT_CAM_UFDI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 13) 183 #define M4U_PORT_CAM_RAWI_R2_B MTK_M4U_ID(M4U_LARB10_ID, 14) 184 #define M4U_PORT_CAM_RAWI_R5_B MTK_M4U_ID(M4U_LARB10_ID, 15) 185 #define M4U_PORT_CAM_CAMSV_0 MTK_M4U_ID(M4U_LARB10_ID, 16) 186 #define M4U_PORT_CAM_AAO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 17) 187 #define M4U_PORT_CAM_AFO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 18) 188 #define M4U_PORT_CAM_FLKO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 19) 189 #define M4U_PORT_CAM_LCESO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 20) 190 #define M4U_PORT_CAM_CRZO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 21) 191 #define M4U_PORT_CAM_AAO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 22) 192 #define M4U_PORT_CAM_AFO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 23) 193 #define M4U_PORT_CAM_FLKO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 24) 194 #define M4U_PORT_CAM_LCESO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 25) 195 #define M4U_PORT_CAM_CRZO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 26) 196 #define M4U_PORT_CAM_LTMSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 27) 197 #define M4U_PORT_CAM_RSSO_R1_A MTK_M4U_ID(M4U_LARB10_ID, 28) 198 #define M4U_PORT_CAM_LTMSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 29) 199 #define M4U_PORT_CAM_RSSO_R1_B MTK_M4U_ID(M4U_LARB10_ID, 30) 200 201 /* larb11-CAM-VPU */ 202 #define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB11_ID, 0) 203 #define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB11_ID, 1) 204 #define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB11_ID, 2) 205 #define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB11_ID, 3) 206 #define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB11_ID, 4) 207 208 #endif 209
Indexes created Tue Sep 30 11:09:46 GMT 2025