| /src/external/gpl3/binutils/dist/opcodes/ |
| spu-opc.c | 1 /* SPU opcode list
22 #include "opcode/spu.h"
24 /* This file holds the Spu opcode table */
30 id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
36 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
39 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
40 #include "opcode/spu-insns.h"
|
| aarch64-tbl.h | 1 /* aarch64-tbl.h -- AArch64 opcode description table and instruction
2836 /* Opcode table. */
3251 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
3252 { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
3253 #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
3254 { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
3255 #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
3256 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
3257 #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \
3258 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| spu-opc.c | 1 /* SPU opcode list
22 #include "opcode/spu.h"
24 /* This file holds the Spu opcode table */
30 id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
36 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
39 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
40 #include "opcode/spu-insns.h"
|
| aarch64-tbl.h | 1 /* aarch64-tbl.h -- AArch64 opcode description table and instruction
2795 /* Opcode table. */
3126 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
3127 { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
3128 #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
3129 { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
3130 #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
3131 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
3132 #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \
3133 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| spu-opc.c | 1 /* SPU opcode list
22 #include "opcode/spu.h"
24 /* This file holds the Spu opcode table */
30 id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
36 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
39 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
40 #include "opcode/spu-insns.h"
|
| aarch64-tbl.h | 1 /* aarch64-tbl.h -- AArch64 opcode description table and instruction
2688 /* Opcode table.
2955 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
2956 { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
2957 #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
2958 { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, 0, NULL }
2959 #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
2960 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL }
2961 #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \
2962 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| spu-opc.c | 1 /* SPU opcode list
22 #include "opcode/spu.h"
24 /* This file holds the Spu opcode table */
30 id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
36 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
39 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
40 #include "opcode/spu-insns.h"
|
| aarch64-tbl.h | 1 /* aarch64-tbl.h -- AArch64 opcode description table and instruction
2795 /* Opcode table. */
3126 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
3127 { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
3128 #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
3129 { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
3130 #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
3131 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
3132 #define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \
3133 { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Analysis/ |
| InstCount.cpp | 31 #define HANDLE_INST(N, OPCODE, CLASS) \
32 STATISTIC(Num##OPCODE##Inst, "Number of " #OPCODE " insts");
43 #define HANDLE_INST(N, OPCODE, CLASS) \
44 void visit##OPCODE(CLASS &) { \
45 ++Num##OPCODE##Inst; \
|
| /src/external/gpl3/gcc/dist/libgcc/config/mips/ |
| mips16.S | 105 /* Jump to T, and use "OPCODE, OP2" to implement a delayed move. */
106 #define DELAYt(T, OPCODE, OP2) \
109 OPCODE, OP2; \
114 #define DELAYf(T, OPCODE, OP2) DELAYt (T, OPCODE, OP2)
116 /* Use "OPCODE. OP2" and jump to T. */
117 #define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
230 performs FPU operation OPCODE on them, and returns the single-
233 #define OPSF3(NAME, OPCODE) \
[all...] |
| /src/external/gpl3/gcc.old/dist/libgcc/config/mips/ |
| mips16.S | 105 /* Jump to T, and use "OPCODE, OP2" to implement a delayed move. */
106 #define DELAYt(T, OPCODE, OP2) \
109 OPCODE, OP2; \
114 #define DELAYf(T, OPCODE, OP2) DELAYt (T, OPCODE, OP2)
116 /* Use "OPCODE. OP2" and jump to T. */
117 #define DELAYf(T, OPCODE, OP2) OPCODE, OP2; jr T
230 performs FPU operation OPCODE on them, and returns the single-
233 #define OPSF3(NAME, OPCODE) \
[all...] |
| /src/external/gpl3/gcc/dist/gcc/config/rs6000/ |
| amo.h | 56 The LWAT/LDAT opcode requires the address to be a single register, and that
60 #define _AMO_LD_SIMPLE(NAME, TYPE, OPCODE, FC) \
67 "\t" OPCODE " %1,%P0,%4\n" \
116 The STWAT/STDAT opcode requires the address to be a single register, and
120 #define _AMO_ST_SIMPLE(NAME, TYPE, OPCODE, FC) \
124 __asm__ volatile (OPCODE " %1,%P0,%2" \
|
| /src/external/gpl3/gcc.old/dist/gcc/config/rs6000/ |
| amo.h | 56 The LWAT/LDAT opcode requires the address to be a single register, and that
60 #define _AMO_LD_SIMPLE(NAME, TYPE, OPCODE, FC) \
67 "\t" OPCODE " %1,%P0,%4\n" \
116 The STWAT/STDAT opcode requires the address to be a single register, and
120 #define _AMO_ST_SIMPLE(NAME, TYPE, OPCODE, FC) \
124 __asm__ volatile (OPCODE " %1,%P0,%2" \
|
| /src/external/gpl3/binutils/dist/include/opcode/ |
| spu.h | 72 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
76 #include "opcode/spu-insns.h"
85 unsigned int opcode; member in struct:spu_opcode
|
| h8300.h | 0 /* Opcode table for the H8/300
617 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
618 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
619 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
620 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
621 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
622 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
623 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
624 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
625 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}},
[all...] |
| /src/external/gpl3/binutils.old/dist/include/opcode/ |
| spu.h | 72 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
76 #include "opcode/spu-insns.h"
85 unsigned int opcode; member in struct:spu_opcode
|
| h8300.h | 0 /* Opcode table for the H8/300
617 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
618 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
619 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
620 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
621 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
622 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
623 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
624 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
625 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}},
[all...] |
| /src/external/gpl3/gdb.old/dist/include/opcode/ |
| spu.h | 72 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
76 #include "opcode/spu-insns.h"
85 unsigned int opcode; member in struct:spu_opcode
|
| h8300.h | 0 /* Opcode table for the H8/300
617 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
618 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
619 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
620 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
621 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
622 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
623 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
624 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
625 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}},
[all...] |
| /src/external/gpl3/gdb/dist/include/opcode/ |
| spu.h | 72 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
76 #include "opcode/spu-insns.h"
85 unsigned int opcode; member in struct:spu_opcode
|
| h8300.h | 0 /* Opcode table for the H8/300
617 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
618 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
619 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
620 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
621 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
622 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
623 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
624 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
625 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}},
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/IR/ |
| InstVisitor.h | 25 #define HANDLE_INST(NUM, OPCODE, CLASS) class CLASS;
77 /// opcode.
123 #define HANDLE_INST(NUM, OPCODE, CLASS) \
124 case Instruction::OPCODE: return \
126 visit##OPCODE(static_cast<CLASS&>(I));
151 // These functions can also implement fan-out, when a single opcode and
155 #define HANDLE_INST(NUM, OPCODE, CLASS) \
156 RetTy visit##OPCODE(CLASS &I) { \
|
| /src/external/gpl3/binutils/dist/gas/config/ |
| tc-rl78.c | 498 so that we can retain this alignment as we adjust opcode sizes. */
576 0 /* opcode */);
735 opcode (like BRA.S). We store the number of total bytes we need in
737 existing opcode bytes to figure out what actual opcode we need to
773 /* Given the opcode bytes at OP, figure out which opcode it is and
774 return the type of opcode. We use this to re-encode the opcode as
866 /* Estimate how big the opcode is after this relax pass. The retur
[all...] |
| /src/external/gpl3/binutils.old/dist/gas/config/ |
| tc-rl78.c | 498 so that we can retain this alignment as we adjust opcode sizes. */
576 0 /* opcode */);
735 opcode (like BRA.S). We store the number of total bytes we need in
737 existing opcode bytes to figure out what actual opcode we need to
773 /* Given the opcode bytes at OP, figure out which opcode it is and
774 return the type of opcode. We use this to re-encode the opcode as
866 /* Estimate how big the opcode is after this relax pass. The retur
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 38 Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
46 // The opcode that should be used to compare Op0 and Op1.
47 unsigned Opcode;
52 // The mask of CC values that Opcode can produce.
326 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
327 if (getOperationAction(Opcode, VT) == Legal)
328 setOperationAction(Opcode, VT, Expand);
735 Opcode = SystemZISD::BYTE_MASK
[all...] |
