1 /* $NetBSD: ingenic_regs.h,v 1.29 2026/07/26 20:15:17 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 Michael Lorenz 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef INGENIC_REGS_H 30 #define INGENIC_REGS_H 31 32 /* for wbflush() */ 33 #include <mips/locore.h> 34 35 /* UARTs, mostly 16550 compatible with 32bit spaced registers */ 36 #define JZ_UART0 0x10030000 37 #define JZ_UART1 0x10031000 38 #define JZ_UART2 0x10032000 39 #define JZ_UART3 0x10033000 40 #define JZ_UART4 0x10034000 41 42 /* LCD controller base addresses, registers are in jzfb_regs.h */ 43 #define JZ_LCDC0_BASE 0x13050000 44 #define JZ_LCDC1_BASE 0x130a0000 45 46 /* watchdog */ 47 #define JZ_WDOG_TDR 0x10002000 /* compare */ 48 #define JZ_WDOG_TCER 0x10002004 49 #define TCER_ENABLE 0x01 /* enable counter */ 50 #define JZ_WDOG_TCNT 0x10002008 /* 16bit up count */ 51 #define JZ_WDOG_TCSR 0x1000200c 52 #define TCSR_PCK_EN 0x01 /* PCLK */ 53 #define TCSR_RTC_EN 0x02 /* RTCCLK - 32.768kHz */ 54 #define TCSR_EXT_EN 0x04 /* EXTCLK - 48MHz */ 55 #define TCSR_PRESCALE_M 0x38 56 #define TCSR_DIV_1 0x00 57 #define TCSR_DIV_4 0x08 58 #define TCSR_DIV_16 0x10 59 #define TCSR_DIV_64 0x18 60 #define TCSR_DIV_256 0x20 61 #define TCSR_DIV_1024 0x28 62 63 /* timers and PWMs */ 64 #define JZ_TC_TER 0x10002010 /* TC enable reg, ro */ 65 #define JZ_TC_TESR 0x10002014 /* TC enable set reg. */ 66 #define TESR_TCST0 0x0001 /* enable counter 0 */ 67 #define TESR_TCST1 0x0002 /* enable counter 1 */ 68 #define TESR_TCST2 0x0004 /* enable counter 2 */ 69 #define TESR_TCST3 0x0008 /* enable counter 3 */ 70 #define TESR_TCST4 0x0010 /* enable counter 4 */ 71 #define TESR_TCST5 0x0020 /* enable counter 5 */ 72 #define TESR_TCST6 0x0040 /* enable counter 6 */ 73 #define TESR_TCST7 0x0080 /* enable counter 7 */ 74 #define TESR_OST 0x8000 /* enable OST */ 75 #define JZ_TC_TECR 0x10002018 /* TC enable clear reg. */ 76 #define JZ_TC_TFR 0x10002020 77 #define TFR_FFLAG0 0x00000001 /* channel 0 */ 78 #define TFR_FFLAG1 0x00000002 /* channel 1 */ 79 #define TFR_FFLAG2 0x00000004 /* channel 2 */ 80 #define TFR_FFLAG3 0x00000008 /* channel 3 */ 81 #define TFR_FFLAG4 0x00000010 /* channel 4 */ 82 #define TFR_FFLAG5 0x00000020 /* channel 5 */ 83 #define TFR_FFLAG6 0x00000040 /* channel 6 */ 84 #define TFR_FFLAG7 0x00000080 /* channel 7 */ 85 #define TFR_OSTFLAG 0x00008000 /* OS timer */ 86 #define JZ_TC_TFSR 0x10002024 /* timer flag set */ 87 #define JZ_TC_TFCR 0x10002028 /* timer flag clear */ 88 #define JZ_TC_TMR 0x10002030 /* timer flag mask */ 89 #define JZ_TC_TMSR 0x10002034 /* timer flag mask set */ 90 #define JZ_TC_TMCR 0x10002038 /* timer flag mask clear*/ 91 92 #define JZ_TC_TDFR(n) (0x10002040 + (n * 0x10)) /* FULL compare */ 93 #define JZ_TC_TDHR(n) (0x10002044 + (n * 0x10)) /* HALF compare */ 94 #define JZ_TC_TCNT(n) (0x10002048 + (n * 0x10)) /* count */ 95 96 #define JZ_TC_TCSR(n) (0x1000204c + (n * 0x10)) 97 /* same bits as in JZ_WDOG_TCSR */ 98 99 /* operating system timer */ 100 #define JZ_OST_DATA 0x100020e0 /* compare */ 101 #define JZ_OST_CNT_LO 0x100020e4 102 #define JZ_OST_CNT_HI 0x100020e8 103 #define JZ_OST_CTRL 0x100020ec 104 #define OSTC_PCK_EN 0x0001 /* use PCLK */ 105 #define OSTC_RTC_EN 0x0002 /* use RTCCLK */ 106 #define OSTC_EXT_EN 0x0004 /* use EXTCLK */ 107 #define OSTC_PRESCALE_M 0x0038 108 #define OSTC_DIV_1 0x0000 109 #define OSTC_DIV_4 0x0008 110 #define OSTC_DIV_16 0x0010 111 #define OSTC_DIV_64 0x0018 112 #define OSTC_DIV_256 0x0020 113 #define OSTC_DIV_1024 0x0028 114 #define OSTC_SHUTDOWN 0x0200 115 #define OSTC_MODE 0x8000 /* 0 - reset to 0 when = OST_DATA */ 116 #define JZ_OST_CNT_U32 0x100020fc /* copy of CNT_HI when reading CNT_LO */ 117 118 static inline void 119 writereg(uint32_t reg, uint32_t val) 120 { 121 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg) = val; 122 wbflush(); 123 } 124 125 static inline uint32_t 126 readreg(uint32_t reg) 127 { 128 wbflush(); 129 return *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(reg); 130 } 131 132 133 /* power management */ 134 #define JZ_CPCCR 0x10000000 /* Clock Control Register */ 135 #define JZ_PDIV_M 0x000f0000 /* PCLK divider mask */ 136 #define JZ_PDIV_S 16 /* PCLK divider shift */ 137 #define JZ_CDIV_M 0x0000000f /* CPU clock divider mask */ 138 #define JZ_CDIV_S 0 /* CPU clock divider shift */ 139 #define JZ_LPCR 0x10000004 /* Low Power Control Register */ 140 #define JZ_PD_SCPU 0x80000000 /* power down 2nd CPU */ 141 #define JZ_SCPUS 0x08000000 /* CPU is powered down */ 142 #define JZ_CPMPCR 0x10000014 /* MPLL */ 143 #define JZ_PLLM_S 19 /* PLL multiplier shift */ 144 #define JZ_PLLM_M 0xfff80000 /* PLL multiplier mask */ 145 #define JZ_PLLN_S 13 /* PLL divider shift */ 146 #define JZ_PLLN_M 0x0007e000 /* PLL divider mask */ 147 #define JZ_PLLP_S 9 /* PLL postdivider shift */ 148 #define JZ_PLLP_M 0x00001700 /* PLL postdivider mask */ 149 #define JZ_PLLON 0x00000010 /* PLL is on and stable */ 150 #define JZ_PLLBP 0x00000002 /* PLL bypass */ 151 #define JZ_PLLEN 0x00000001 /* PLL enable */ 152 #define JZ_CPVPCR 0x1000001c /* VPLL */ 153 #define JZ_CLKGR0 0x10000020 /* CLocK Gating Registers */ 154 #define CLK_NEMC (1 << 0) 155 #define CLK_BCH (1 << 1) 156 #define CLK_OTG0 (1 << 2) 157 #define CLK_MSC0 (1 << 3) 158 #define CLK_SSI0 (1 << 4) 159 #define CLK_SMB0 (1 << 5) 160 #define CLK_SMB1 (1 << 6) 161 #define CLK_SCC (1 << 7) 162 #define CLK_AIC (1 << 8) 163 #define CLK_TSSI0 (1 << 9) 164 #define CLK_OWI (1 << 10) 165 #define CLK_MSC1 (1 << 11) 166 #define CLK_MSC2 (1 << 12) 167 #define CLK_KBC (1 << 13) 168 #define CLK_SADC (1 << 14) 169 #define CLK_UART0 (1 << 15) 170 #define CLK_UART1 (1 << 16) 171 #define CLK_UART2 (1 << 17) 172 #define CLK_UART3 (1 << 18) 173 #define CLK_SSI1 (1 << 19) 174 #define CLK_SSI2 (1 << 20) 175 #define CLK_PDMA (1 << 21) 176 #define CLK_GPS (1 << 22) 177 #define CLK_MAC (1 << 23) 178 #define CLK_UHC (1 << 24) 179 #define CLK_SMB2 (1 << 25) 180 #define CLK_CIM (1 << 26) 181 #define CLK_TVE (1 << 27) 182 #define CLK_LCD (1 << 28) 183 #define CLK_IPU (1 << 29) 184 #define CLK_DDR0 (1 << 30) 185 #define CLK_DDR1 (1 << 31) 186 187 #define JZ_OPCR 0x10000024 /* Oscillator Power Control Reg. */ 188 #define OPCR_IDLE_DIS 0x80000000 /* don't stop CPU clk on idle */ 189 #define OPCR_GPU_CLK_ST 0x40000000 /* stop GPU clock */ 190 #define OPCR_L2CM_M 0x0c000000 191 #define OPCR_L2CM_ON 0x00000000 /* L2 stays on in sleep */ 192 #define OPCR_L2CM_RET 0x04000000 /* L2 retention mode in sleep */ 193 #define OPCR_L2CM_OFF 0x08000000 /* L2 powers down in sleep */ 194 #define OPCR_SPENDN0 0x00000080 /* 0 - OTG port forced down */ 195 #define OPCR_SPENDN1 0x00000040 /* 0 - UHC port forced down */ 196 #define OPCR_BUS_MODE 0x00000020 /* 1 - bursts */ 197 #define OPCR_O1SE 0x00000010 /* EXTCLK on in sleep */ 198 #define OPCR_PD 0x00000008 /* P0 down in sleep */ 199 #define OPCR_ERCS 0x00000004 /* 1 RTCCLK, 0 EXTCLK/512 */ 200 #define OPCR_CPU_MODE 0x00000002 /* 1 access 'accelerated' */ 201 #define OPCR_OSE 0x00000001 /* disable EXTCLK */ 202 #define JZ_CLKGR1 0x10000028 /* CLocK Gating Registers */ 203 #define CLK_SMB3 (1 << 0) 204 #define CLK_TSSI1 (1 << 1) 205 #define CLK_VPU (1 << 2) 206 #define CLK_PCM (1 << 3) 207 #define CLK_GPU (1 << 4) 208 #define CLK_COMPRESS (1 << 5) 209 #define CLK_AIC1 (1 << 6) 210 #define CLK_GPVLC (1 << 7) 211 #define CLK_OTG1 (1 << 8) 212 #define CLK_HDMI (1 << 9) 213 #define CLK_UART4 (1 << 10) 214 #define CLK_AHB_MON (1 << 11) 215 #define CLK_SMB4 (1 << 12) 216 #define CLK_DES (1 << 13) 217 #define CLK_X2D (1 << 14) 218 #define CLK_P1 (1 << 15) 219 220 #define JZ_USBPCR 0x1000003c 221 #define PCR_USB_MODE 0x80000000 /* 1 - otg */ 222 #define PCR_AVLD_REG 0x40000000 223 #define PCR_IDPULLUP_MASK 0x30000000 224 #define PCR_INCR_MASK 0x08000000 225 #define PCR_TCRISETUNE 0x04000000 226 #define PCR_COMMONONN 0x02000000 227 #define PCR_VBUSVLDEXT 0x01000000 228 #define PCR_VBUSVLDEXTSEL 0x00800000 229 #define PCR_POR 0x00400000 230 #define PCR_SIDDQ 0x00200000 231 #define PCR_OTG_DISABLE 0x00100000 232 #define PCR_COMPDISTN_M 0x000e0000 233 #define PCR_OTGTUNE 0x0001c000 234 #define PCR_SQRXTUNE 0x00003800 235 #define PCR_TXFSLSTUNE 0x00000780 236 #define PCR_TXPREEMPHTUNE 0x00000040 237 #define PCR_TXHSXVTUNE 0x00000030 238 #define PCR_TXVREFTUNE 0x0000000f 239 #define JZ_USBRDT 0x10000040 /* Reset Detect Timer Register */ 240 #define JZ_USBVBFIL 0x10000044 241 #define JZ_USBPCR1 0x10000048 242 #define PCR_SYNOPSYS 0x10000000 /* Mentor mode otherwise */ 243 #define PCR_REFCLK_CORE 0x0c000000 244 #define PCR_REFCLK_XO25 0x04000000 245 #define PCR_REFCLK_CO 0x00000000 246 #define PCR_CLK_M 0x03000000 /* clock */ 247 #define PCR_CLK_192 0x03000000 /* 19.2MHz */ 248 #define PCR_CLK_48 0x02000000 /* 48MHz */ 249 #define PCR_CLK_24 0x01000000 /* 24MHz */ 250 #define PCR_CLK_12 0x00000000 /* 12MHz */ 251 #define PCR_DMPD1 0x00800000 /* pull down D- on port 1 */ 252 #define PCR_DPPD1 0x00400000 /* pull down D+ on port 1 */ 253 #define PCR_PORT0_RST 0x00200000 /* port 0 reset */ 254 #define PCR_PORT1_RST 0x00100000 /* port 1 reset */ 255 #define PCR_WORD_I_F0 0x00080000 /* 1: 16bit/30M, 8/60 otherw. */ 256 #define PCR_WORD_I_F1 0x00040000 /* same for port 1 */ 257 #define PCR_COMPDISTUNE 0x00038000 /* disconnect threshold */ 258 #define PCR_SQRXTUNE1 0x00007000 /* squelch threshold */ 259 #define PCR_TXFSLSTUNE1 0x00000f00 /* FS/LS impedance adj. */ 260 #define PCR_TXPREEMPH 0x00000080 /* HS transm. pre-emphasis */ 261 #define PCR_TXHSXVTUNE1 0x00000060 /* dp/dm voltage adj. */ 262 #define PCR_TXVREFTUNE1 0x00000017 /* HS DC voltage adj. */ 263 #define PCR_TXRISETUNE1 0x00000001 /* rise/fall wave adj. */ 264 265 #define JZ_UHCCDR 0x1000006c /* UHC Clock Divider Register */ 266 #define UHCCDR_SCLK_A 0x00000000 267 #define UHCCDR_MPLL 0x40000000 268 #define UHCCDR_EPLL 0x80000000 269 #define UHCCDR_OTG_PHY 0xc0000000 270 #define UHCCDR_CE 0x20000000 271 #define UHCCDR_BUSY 0x10000000 272 #define UHCCDR_STOP 0x08000000 273 #define UHCCDR_DIV_M 0x000000ff 274 #define JZ_SPCR0 0x100000b8 /* SRAM Power Control Registers */ 275 #define JZ_SPCR1 0x100000bc 276 #define JZ_SRBC 0x100000c4 /* Soft Reset & Bus Control */ 277 278 /* clock divider registers, handshake bits common to all of them */ 279 #define CDR_CE 0x20000000 /* change enable */ 280 #define CDR_BUSY 0x10000000 /* divider update in progress */ 281 #define JZ_MSC0CDR 0x10000068 282 #define MSCCDR_SCLK_A 0x40000000 283 #define MSCCDR_MPLL 0x80000000 284 #define MSCCDR_CE 0x20000000 285 #define MSCCDR_BUSY 0x10000000 286 #define MSCCDR_STOP 0x08000000 287 #define MSCCDR_PHASE 0x00008000 /* 0 - 90deg phase, 1 - 180 */ 288 #define MSCCDR_DIV_M 0x000000ff /* src / ((div + 1) * 2) */ 289 #define UHCCDR_DIV_M 0x000000ff 290 #define JZ_MSC1CDR 0x100000a4 291 #define JZ_MSC2CDR 0x100000a8 292 293 /* 294 * random number generator 295 * 296 * Its function currently isn't documented by Ingenic. 297 * However, testing suggests that it works as expected. 298 */ 299 #define JZ_ERNG 0x100000d8 300 #define JZ_RNG 0x100000dc 301 302 /* interrupt controller */ 303 #define JZ_ICSR0 0x10001000 /* raw IRQ line status */ 304 #define JZ_ICMR0 0x10001004 /* IRQ mask, 1 masks IRQ */ 305 #define JZ_ICMSR0 0x10001008 /* sets bits in mask register */ 306 #define JZ_ICMCR0 0x1000100c /* clears bits in mask register */ 307 #define JZ_ICPR0 0x10001010 /* line status after masking */ 308 309 #define JZ_ICSR1 0x10001020 /* raw IRQ line status */ 310 #define JZ_ICMR1 0x10001024 /* IRQ mask, 1 masks IRQ */ 311 #define JZ_ICMSR1 0x10001028 /* sets bits in mask register */ 312 #define JZ_ICMCR1 0x1000102c /* clears bits in mask register */ 313 #define JZ_ICPR1 0x10001030 /* line status after masking */ 314 315 #define JZ_DSR0 0x10001034 /* source for PDMA */ 316 #define JZ_DMR0 0x10001038 /* mask for PDMA */ 317 #define JZ_DPR0 0x1000103c /* pending for PDMA */ 318 319 #define JZ_DSR1 0x10001040 /* source for PDMA */ 320 #define JZ_DMR1 0x10001044 /* mask for PDMA */ 321 #define JZ_DPR1 0x10001048 /* pending for PDMA */ 322 323 /* memory controller */ 324 #define JZ_DMMAP0 0x13010024 325 #define JZ_DMMAP1 0x13010028 326 #define DMMAP_BASE 0x0000ff00 /* base PADDR of memory chunk */ 327 #define DMMAP_MASK 0x000000ff /* mask which bits of PADDR are 328 * constant */ 329 /* USB controllers */ 330 #define JZ_EHCI_BASE 0x13490000 331 #define JZ_OHCI_BASE 0x134a0000 332 #define JZ_DWC2_BASE 0x13500000 333 334 /* Ethernet */ 335 #define JZ_DME_BASE 0x16000000 336 #define JZ_DME_IO 0 337 #define JZ_DME_DATA 2 338 339 /* GPIO */ 340 #define JZ_GPIO_A_BASE 0x10010000 341 #define JZ_GPIO_B_BASE 0x10010100 342 #define JZ_GPIO_C_BASE 0x10010200 343 #define JZ_GPIO_D_BASE 0x10010300 344 #define JZ_GPIO_E_BASE 0x10010400 345 #define JZ_GPIO_F_BASE 0x10010500 346 347 /* GPIO registers per port */ 348 #define JZ_GPIO_PIN 0x00000000 /* pin level register */ 349 /* 0 - normal gpio, 1 - interrupt */ 350 #define JZ_GPIO_INT 0x00000010 /* interrupt register */ 351 #define JZ_GPIO_INTS 0x00000014 /* interrupt set register */ 352 #define JZ_GPIO_INTC 0x00000018 /* interrupt clear register */ 353 /* 354 * INT == 1: 1 disables interrupt 355 * INT == 0: device select, see below 356 */ 357 #define JZ_GPIO_MASK 0x00000020 /* port mask register */ 358 #define JZ_GPIO_MASKS 0x00000024 /* port mask set register */ 359 #define JZ_GPIO_MASKC 0x00000028 /* port mask clear register */ 360 /* 361 * INT == 1: 0 - level triggered, 1 - edge triggered 362 * INT == 0: 0 - device select, see below 363 */ 364 #define JZ_GPIO_PAT1 0x00000030 /* pattern 1 register */ 365 #define JZ_GPIO_PAT1S 0x00000034 /* pattern 1 set register */ 366 #define JZ_GPIO_PAT1C 0x00000038 /* pattern 1 clear register */ 367 /* 368 * INT == 1: 369 * PAT1 == 0: 0 - trigger on low, 1 - trigger on high 370 * PAT1 == 1: 0 - trigger on falling edge, 1 - trigger on rising edge 371 * INT == 0: 372 * MASK == 0: 373 * PAT1 == 0: 0 - device 0, 1 - device 1 374 * PAT1 == 1: 0 - device 2, 1 - device 3 375 * MASK == 1: 376 * PAT1 == 0: set gpio output 377 * PAT1 == 1: pin is input 378 */ 379 #define JZ_GPIO_PAT0 0x00000040 /* pattern 0 register */ 380 #define JZ_GPIO_PAT0S 0x00000044 /* pattern 0 set register */ 381 #define JZ_GPIO_PAT0C 0x00000048 /* pattern 0 clear register */ 382 /* 1 - interrupt happened */ 383 #define JZ_GPIO_FLAG 0x00000050 /* flag register */ 384 #define JZ_GPIO_FLAGC 0x00000058 /* flag clear register */ 385 /* 1 - disable pull up/down resistors */ 386 #define JZ_GPIO_DPULL 0x00000070 /* pull disable register */ 387 #define JZ_GPIO_DPULLS 0x00000074 /* pull disable set register */ 388 #define JZ_GPIO_DPULLC 0x00000078 /* pull disable clear register */ 389 /* the following are uncommented in the manual */ 390 #define JZ_GPIO_DRVL 0x00000080 /* drive low register */ 391 #define JZ_GPIO_DRVLS 0x00000084 /* drive low set register */ 392 #define JZ_GPIO_DRVLC 0x00000088 /* drive low clear register */ 393 #define JZ_GPIO_DIR 0x00000090 /* direction register */ 394 #define JZ_GPIO_DIRS 0x00000094 /* direction register */ 395 #define JZ_GPIO_DIRC 0x00000098 /* direction register */ 396 #define JZ_GPIO_DRVH 0x000000a0 /* drive high register */ 397 #define JZ_GPIO_DRVHS 0x000000a4 /* drive high set register */ 398 #define JZ_GPIO_DRVHC 0x000000a8 /* drive high clear register */ 399 400 static inline void 401 gpio_as_output(uint32_t g, int pin) 402 { 403 uint32_t mask = 1 << pin; 404 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 405 406 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 407 writereg(reg + JZ_GPIO_MASKS, mask); 408 writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */ 409 } 410 411 static inline void 412 gpio_set(uint32_t g, int pin, int level) 413 { 414 uint32_t mask = 1 << pin; 415 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 416 417 reg += (level == 0) ? JZ_GPIO_PAT0C : JZ_GPIO_PAT0S; 418 writereg(reg, mask); 419 } 420 421 static inline bool 422 gpio_get(uint32_t g, int pin) 423 { 424 uint32_t mask = 1 << pin; 425 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 426 427 return (readreg(reg + JZ_GPIO_PIN) & mask) != 0; 428 } 429 430 static inline void 431 gpio_as_dev0(uint32_t g, int pin) 432 { 433 uint32_t mask = 1 << pin; 434 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 435 436 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 437 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 438 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */ 439 writereg(reg + JZ_GPIO_PAT0C, mask); 440 } 441 442 static inline void 443 gpio_as_dev1(uint32_t g, int pin) 444 { 445 uint32_t mask = 1 << pin; 446 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 447 448 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 449 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 450 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 1 */ 451 writereg(reg + JZ_GPIO_PAT0S, mask); 452 } 453 454 static inline void 455 gpio_as_dev2(uint32_t g, int pin) 456 { 457 uint32_t mask = 1 << pin; 458 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 459 460 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 461 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 462 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 2 */ 463 writereg(reg + JZ_GPIO_PAT0C, mask); 464 } 465 466 static inline void 467 gpio_as_dev3(uint32_t g, int pin) 468 { 469 uint32_t mask = 1 << pin; 470 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 471 472 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */ 473 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */ 474 writereg(reg + JZ_GPIO_PAT1S, mask); /* select 3 */ 475 writereg(reg + JZ_GPIO_PAT0S, mask); 476 } 477 478 static inline void 479 gpio_as_intr_level(uint32_t g, int pin) 480 { 481 uint32_t mask = 1 << pin; 482 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 483 484 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */ 485 writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */ 486 writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */ 487 writereg(reg + JZ_GPIO_PAT0S, mask); /* trigger on high */ 488 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */ 489 writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */ 490 } 491 492 static inline void 493 gpio_as_intr_level_low(uint32_t g, int pin) 494 { 495 uint32_t mask = 1 << pin; 496 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 497 498 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */ 499 writereg(reg + JZ_GPIO_INTS, mask); /* use as interrupt */ 500 writereg(reg + JZ_GPIO_PAT1C, mask); /* level trigger */ 501 writereg(reg + JZ_GPIO_PAT0C, mask); /* trigger on low */ 502 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it */ 503 writereg(reg + JZ_GPIO_MASKC, mask); /* enable it */ 504 } 505 506 static inline void 507 gpio_as_input(uint32_t g, int pin) 508 { 509 uint32_t mask = 1 << pin; 510 uint32_t reg = JZ_GPIO_A_BASE + (g << 8); 511 512 writereg(reg + JZ_GPIO_MASKS, mask); /* mask it */ 513 writereg(reg + JZ_GPIO_INTC, mask); /* not an interrupt */ 514 writereg(reg + JZ_GPIO_PAT1S, mask); /* use as input */ 515 writereg(reg + JZ_GPIO_FLAGC, mask); /* clear it just in case */ 516 } 517 518 /* I2C / SMBus */ 519 #define JZ_SMB0_BASE 0x10050000 520 #define JZ_SMB1_BASE 0x10051000 521 #define JZ_SMB2_BASE 0x10052000 522 #define JZ_SMB3_BASE 0x10053000 523 #define JZ_SMB4_BASE 0x10054000 524 525 /* SMBus register offsets, per port */ 526 #define JZ_SMBCON 0x00 /* SMB control */ 527 #define JZ_STPHLD 0x80 /* Stop Hold Enable bit */ 528 #define JZ_SLVDIS 0x40 /* 1 - slave disabled */ 529 #define JZ_REST 0x20 /* 1 - allow RESTART */ 530 #define JZ_MATP 0x10 /* 1 - enable 10bit addr. for master */ 531 #define JZ_SATP 0x08 /* 1 - enable 10bit addr. for slave */ 532 #define JZ_SPD_M 0x06 /* bus speed control */ 533 #define JZ_SPD_100KB 0x02 /* 100kBit/s mode */ 534 #define JZ_SPD_400KB 0x04 /* 400kBit/s mode */ 535 #define JZ_MD 0x01 /* enable master */ 536 #define JZ_SMBTAR 0x04 /* SMB target address */ 537 #define JZ_SMATP 0x1000 /* enable 10bit master addr */ 538 #define JZ_SPECIAL 0x0800 /* 1 - special command */ 539 #define JZ_START 0x0400 /* 1 - send START */ 540 #define JZ_SMBTAR_M 0x03ff /* target address */ 541 #define JZ_SMBSAR 0x08 /* SMB slave address */ 542 #define JZ_SMBDC 0x10 /* SMB data buffer and command */ 543 #define JZ_CMD 0x100 /* 1 - read, 0 - write */ 544 #define JZ_DATA 0x0ff 545 #define JZ_SMBSHCNT 0x14 /* Standard speed SMB SCL high count */ 546 #define JZ_SMBSLCNT 0x18 /* Standard speed SMB SCL low count */ 547 #define JZ_SMBFHCNT 0x1C /* Fast speed SMB SCL high count */ 548 #define JZ_SMBFLCNT 0x20 /* Fast speed SMB SCL low count */ 549 #define JZ_SMBINTST 0x2C /* SMB Interrupt Status */ 550 #define JZ_ISTT 0x400 /* START or RESTART occurred */ 551 #define JZ_ISTP 0x200 /* STOP occurred */ 552 #define JZ_TXABT 0x40 /* ABORT occurred */ 553 #define JZ_TXEMP 0x10 /* TX FIFO is low */ 554 #define JZ_TXOF 0x08 /* TX FIFO is high */ 555 #define JZ_RXFL 0x04 /* RX FIFO is at JZ_SMBRXTL*/ 556 #define JZ_RXOF 0x02 /* RX FIFO is high */ 557 #define JZ_RXUF 0x01 /* RX FIFO underflow */ 558 #define JZ_SMBINTM 0x30 /* SMB Interrupt Mask */ 559 #define JZ_SMBRXTL 0x38 /* SMB RxFIFO Threshold */ 560 #define JZ_SMBTXTL 0x3C /* SMB TxFIFO Threshold */ 561 #define JZ_SMBCINT 0x40 /* Clear Interrupts */ 562 #define JZ_CLEARALL 0x01 563 #define JZ_SMBCRXUF 0x44 /* Clear RXUF Interrupt */ 564 #define JZ_SMBCRXOF 0x48 /* Clear RX_OVER Interrupt */ 565 #define JZ_SMBCTXOF 0x4C /* Clear TX_OVER Interrupt */ 566 #define JZ_SMBCRXREQ 0x50 /* Clear RDREQ Interrupt */ 567 #define JZ_SMBCTXABT 0x54 /* Clear TX_ABRT Interrupt */ 568 #define JZ_SMBCRXDN 0x58 /* Clear RX_DONE Interrupt */ 569 #define JZ_SMBCACT 0x5c /* Clear ACTIVITY Interrupt */ 570 #define JZ_SMBCSTP 0x60 /* Clear STOP Interrupt */ 571 #define JZ_SMBCSTT 0x64 /* Clear START Interrupt */ 572 #define JZ_SMBCGC 0x68 /* Clear GEN_CALL Interrupt */ 573 #define JZ_SMBENB 0x6C /* SMB Enable */ 574 #define JZ_ENABLE 0x01 575 #define JZ_SMBST 0x70 /* SMB Status register */ 576 #define JZ_SLVACT 0x40 /* slave is active */ 577 #define JZ_MSTACT 0x20 /* master is active */ 578 #define JZ_RFF 0x10 /* RX FIFO is full */ 579 #define JZ_RFNE 0x08 /* RX FIFO not empty */ 580 #define JZ_TFE 0x04 /* TX FIFO is empty */ 581 #define JZ_TFNF 0x02 /* TX FIFO is not full */ 582 #define JZ_ACT 0x01 /* JZ_SLVACT | JZ_MSTACT */ 583 #define JZ_SMBABTSRC 0x80 /* SMB Transmit Abort Status Register */ 584 #define JZ_SMBDMACR 0x88 /* DMA Control Register */ 585 #define JZ_SMBDMATDL 0x8c /* DMA Transmit Data Level */ 586 #define JZ_SMBDMARDL 0x90 /* DMA Receive Data Level */ 587 #define JZ_SMBSDASU 0x94 /* SMB SDA Setup Register */ 588 #define JZ_SMBACKGC 0x98 /* SMB ACK General Call Register */ 589 #define JZ_SMBENBST 0x9C /* SMB Enable Status Register */ 590 #define JZ_SMBSDAHD 0xD0 /* SMB SDA HolD time Register */ 591 #define JZ_HDENB 0x100 /* enable hold time */ 592 593 /* SD/MMC hosts */ 594 #define JZ_MSC0_BASE 0x13450000 595 #define JZ_MSC1_BASE 0x13460000 596 #define JZ_MSC2_BASE 0x13470000 597 598 #define JZ_MSC_CTRL 0x00 599 #define JZ_SEND_CCSD 0x8000 600 #define JZ_SEND_AS_CCSD 0x4000 601 #define JZ_EXIT_MULTIPLE 0x0080 602 #define JZ_EXIT_TRANSFER 0x0040 603 #define JZ_START_READWAIT 0x0020 604 #define JZ_STOP_READWAIT 0x0010 605 #define JZ_RESET 0x0008 606 #define JZ_START_OP 0x0004 607 #define JZ_CLOCK_CTRL_M 0x0003 608 #define JZ_CLOCK_START 0x0002 609 #define JZ_CLOCK_STOP 0x0001 610 #define JZ_MSC_STAT 0x04 611 #define JZ_AUTO_CMD12_DONE 0x80000000 612 #define JZ_AUTO_CMD23_DONE 0x40000000 613 #define JZ_SVS 0x20000000 614 #define JZ_PIN_LEVEL_M 0x1f000000 615 #define JZ_BCE 0x00100000 /* boot CRC error */ 616 #define JZ_BDE 0x00080000 /* boot data end */ 617 #define JZ_BAE 0x00040000 /* boot acknowledge error */ 618 #define JZ_BAR 0x00020000 /* boot ack. received */ 619 #define JZ_DMAEND 0x00010000 620 #define JZ_IS_RESETTING 0x00008000 621 #define JZ_SDIO_INT_ACTIVE 0x00004000 622 #define JZ_PRG_DONE 0x00002000 623 #define JZ_DATA_TRAN_DONE 0x00001000 624 #define JZ_END_CMD_RES 0x00000800 625 #define JZ_DATA_FIFO_AFULL 0x00000400 626 #define JZ_IS_READWAIT 0x00000200 627 #define JZ_CLK_EN 0x00000100 628 #define JZ_DATA_FIFO_FULL 0x00000080 629 #define JZ_DATA_FIFO_EMPTY 0x00000040 630 #define JZ_CRC_RES_ERR 0x00000020 631 #define JZ_CRC_READ_ERR 0x00000010 632 #define JZ_CRC_WRITE_ERR_M 0x0000000c 633 #define JZ_CRC_WRITE_OK 0x00000000 634 #define JZ_CRC_CARD_ERR 0x00000004 635 #define JZ_CRC_NO_STATUS 0x00000008 636 #define JZ_TIME_OUT_RES 0x00000002 637 #define JZ_TIME_OUT_READ 0x00000001 638 #define JZ_MSC_CLKRT 0x08 639 #define JZ_DEV_CLK 0x0 640 #define JZ_DEV_CLK_2 0x1 /* DEV_CLK / 2 */ 641 #define JZ_DEV_CLK_4 0x2 /* DEV_CLK / 4 */ 642 #define JZ_DEV_CLK_8 0x3 /* DEV_CLK / 8 */ 643 #define JZ_DEV_CLK_16 0x4 /* DEV_CLK / 16 */ 644 #define JZ_DEV_CLK_32 0x5 /* DEV_CLK / 32 */ 645 #define JZ_DEV_CLK_64 0x6 /* DEV_CLK / 64 */ 646 #define JZ_DEV_CLK_128 0x7 /* DEV_CLK / 128 */ 647 #define JZ_MSC_CMDAT 0x0c 648 #define JZ_CCS_EXPECTED 0x80000000 649 #define JZ_READ_CEATA 0x40000000 650 #define JZ_DIS_BOOT 0x08000000 651 #define JZ_ENA_BOOT 0x04000000 652 #define JZ_EXP_BOOT_ACK 0x02000000 653 #define JZ_BOOT_MODE 0x01000000 654 #define JZ_AUTO_CMD23 0x00040000 655 #define JZ_SDIO_PRDT 0x00020000 656 #define JZ_AUTO_CMD12 0x00010000 657 #define JZ_RTRG_M 0x0000c000 /* receive FIFO trigger */ 658 #define JZ_RTRG_16 0x00000000 /* >= 16 */ 659 #define JZ_RTRG_32 0x00004000 /* >= 32 */ 660 #define JZ_RTRG_64 0x00008000 /* >= 64 */ 661 #define JZ_RTRG_96 0x0000c000 /* >= 96 */ 662 #define JZ_TTRG_M 0x00003000 /* transmit FIFO trigger */ 663 #define JZ_TTRG_16 0x00000000 /* >= 16 */ 664 #define JZ_TTRG_32 0x00001000 /* >= 32 */ 665 #define JZ_TTRG_64 0x00002000 /* >= 64 */ 666 #define JZ_TTRG_96 0x00003000 /* >= 96 */ 667 #define JZ_IO_ABORT 0x00000800 668 #define JZ_BUS_WIDTH_M 0x00000600 669 #define JZ_BUS_1BIT 0x00000000 670 #define JZ_BUS_4BIT 0x00000400 /* bit 10 (not 9!), per Linux */ 671 #define JZ_BUS_8BIT 0x00000600 672 #define JZ_INIT 0x00000080 /* send 80 clk init before cmd */ 673 #define JZ_BUSY 0x00000040 674 #define JZ_STREAM 0x00000020 675 #define JZ_WRITE 0x00000010 /* read otherwise */ 676 #define JZ_DATA_EN 0x00000008 677 #define JZ_RESPONSE_M 0x00000007 /* response format */ 678 #define JZ_RES_NONE 0x00000000 679 #define JZ_RES_R1 0x00000001 /* R1 and R1b */ 680 #define JZ_RES_R2 0x00000002 681 #define JZ_RES_R3 0x00000003 682 #define JZ_RES_R4 0x00000004 683 #define JZ_RES_R5 0x00000005 684 #define JZ_RES_R6 0x00000006 685 #define JZ_RES_R7 0x00000007 686 #define JZ_MSC_RESTO 0x10 /* 16bit response timeout in MSC_CLK */ 687 #define JZ_MSC_RDTO 0x14 /* 32bit read timeout in MSC_CLK */ 688 #define JZ_MSC_BLKLEN 0x18 /* 16bit block length */ 689 #define JZ_MSC_NOB 0x1c /* 16bit block counter */ 690 #define JZ_MSC_SNOB 0x20 /* 16bit successful block counter */ 691 #define JZ_MSC_IMASK 0x24 /* interrupt mask */ 692 #define JZ_INT_AUTO_CMD23_DONE 0x40000000 693 #define JZ_INT_SVS 0x20000000 694 #define JZ_INT_PIN_LEVEL_M 0x1f000000 695 #define JZ_INT_BCE 0x00100000 696 #define JZ_INT_BDE 0x00080000 697 #define JZ_INT_BAE 0x00040000 698 #define JZ_INT_BAR 0x00020000 699 #define JZ_INT_DMAEND 0x00010000 700 #define JZ_INT_AUTO_CMD12_DONE 0x00008000 701 #define JZ_INT_DATA_FIFO_FULL 0x00004000 702 #define JZ_INT_DATA_FIFO_EMPTY 0x00002000 703 #define JZ_INT_CRC_RES_ERR 0x00001000 704 #define JZ_INT_CRC_READ_ERR 0x00000800 705 #define JZ_INT_CRC_WRITE_ERR 0x00000400 706 #define JZ_INT_TIMEOUT_RES 0x00000200 707 #define JZ_INT_TIMEOUT_READ 0x00000100 708 #define JZ_INT_SDIO 0x00000080 709 #define JZ_INT_TXFIFO_WR_REQ 0x00000040 710 #define JZ_INT_RXFIFO_RD_REQ 0x00000020 711 #define JZ_INT_EMD_CMD_RES 0x00000004 712 #define JZ_INT_PRG_DONE 0x00000002 713 #define JZ_INT_DATA_TRAN_DONE 0x00000001 714 #define JZ_MSC_IFLG 0x28 /* interrupt flags */ 715 #define JZ_MSC_CMD 0x2c /* 6bit CMD index */ 716 #define JZ_MSC_ARG 0x30 /* 32bit argument */ 717 #define JZ_MSC_RES 0x34 /* 8x16bit response data FIFO */ 718 #define JZ_MSC_RXFIFO 0x38 719 #define JZ_MSC_TXFIFO 0x3c 720 #define JZ_MSC_LPM 0x40 721 #define JZ_DRV_SEL_M 0xc0000000 722 #define JZ_FALLING_EDGE 0x00000000 723 #define JZ_RISING_1NS 0x40000000 /* 1ns delay */ 724 #define JZ_RISING_4 0x80000000 /* 1/4 MSC_CLK delay */ 725 #define JZ_SMP_SEL 0x20000000 /* 1 - rising edge */ 726 #define JZ_LPM 0x00000001 /* low power mode */ 727 #define JZ_MSC_DMAC 0x44 728 #define JZ_MODE_SEL 0x80 /* 1 - specify transfer length */ 729 #define JZ_AOFST_M 0x60 /* address offset in bytes */ 730 #define JZ_ALIGNEN 0x10 /* allow non-32bit-aligned transfers */ 731 #define JZ_INCR_M 0x0c /* burst type */ 732 #define JZ_INCR_16 0x00 733 #define JZ_INCR_32 0x04 734 #define JZ_INCR_64 0x08 735 #define JZ_DMASEL 0x02 /* 1 - SoC DMAC, 0 - MSC built-in */ 736 #define JZ_DMAEN 0x01 /* enable DMA */ 737 #define JZ_MSC_DMANDA 0x48 /* next descriptor paddr, 16-byte aligned */ 738 #define JZ_MSC_DMADA 0x4c /* current descriptor data address */ 739 #define JZ_MSC_DMALEN 0x50 /* transfer length */ 740 /* 741 * Read-only shadow of the current descriptor's CMD word 742 */ 743 #define JZ_MSC_DMACMD 0x54 744 #define JZ_DMA_IDI_M 0xff000000 745 #define JZ_DMA_ID_M 0x00ff0000 746 #define JZ_DMA_AOFST_M 0x00000600 747 #define JZ_DMA_ALIGN 0x00000100 748 #define JZ_DMA_ENDI 0x00000002 /* interrupt at this descriptor's end */ 749 #define JZ_DMA_LINK 0x00000001 /* 0 - fetch next from NDA, 1 - end of chain (sets DMAEND) */ 750 #define JZ_MSC_CTRL2 0x58 751 #define JZ_PIP 0x1f000000 /* 1 - intr trigger on high */ 752 #define JZ_RST_EN 0x00800000 753 #define JZ_STPRM 0x00000010 754 #define JZ_SVC 0x00000008 755 #define JZ_SMS_M 0x00000007 756 #define JZ_SMS_DEF 0x00000000 /* default speed */ 757 #define JZ_SMS_HIGH 0x00000001 /* high speed */ 758 #define JZ_SMS_SDR12 0x00000002 759 #define JZ_SMS_SDR25 0x00000003 760 #define JZ_SMS_SDR50 0x00000004 761 #define JZ_MSC_RTCNT 0x5c /* RT FIFO count */ 762 763 /* EFUSE Slave Interface */ 764 #define JZ_EFUSE 0x134100D0 765 #define JZ_EFUCTRL 0x00 766 #define JZ_EFUSE_BANK 0x40000000 /* select upper 4KBit */ 767 #define JZ_EFUSE_ADDR_M 0x3fe00000 /* in bytes */ 768 #define JZ_EFUSE_ADDR_SHIFT 21 769 #define JZ_EFUSE_SIZE_M 0x001f0000 /* in bytes */ 770 #define JZ_EFUSE_SIZE_SHIFT 16 771 #define JZ_EFUSE_PROG 0x00008000 /* enable programming */ 772 #define JZ_EFUSE_WRITE 0x00000002 /* write enable */ 773 #define JZ_EFUSE_READ 0x00000001 /* read enable */ 774 #define JZ_EFUCFG 0x04 775 #define JZ_EFUSE_INT_E 0x80000000 /* which IRQ? */ 776 #define JZ_EFUSE_RD_ADJ_M 0x00f00000 777 #define JZ_EFUSE_RD_STROBE 0x000f0000 778 #define JZ_EFUSE_WR_ADJUST 0x0000f000 779 #define JZ_EFUSE_WR_STROBE 0x00000fff 780 #define JZ_EFUSTATE 0x08 781 #define JZ_EFUSE_GLOBAL_P 0x00008000 /* wr protect bits */ 782 #define JZ_EFUSE_CHIPID_P 0x00004000 783 #define JZ_EFUSE_CUSTID_P 0x00002000 784 #define JZ_EFUSE_SECWR_EN 0x00001000 785 #define JZ_EFUSE_PC_P 0x00000800 786 #define JZ_EFUSE_HDMIKEY_P 0x00000400 787 #define JZ_EFUSE_SECKEY_P 0x00000200 788 #define JZ_EFUSE_SECBOOT_EN 0x00000100 789 #define JZ_EFUSE_HDMI_BUSY 0x00000004 790 #define JZ_EFUSE_WR_DONE 0x00000002 791 #define JZ_EFUSE_RD_DONE 0x00000001 792 #define JZ_EFUDATA0 0x0C 793 #define JZ_EFUDATA1 0x10 794 #define JZ_EFUDATA2 0x14 795 #define JZ_EFUDATA3 0x18 796 #define JZ_EFUDATA4 0x1C 797 #define JZ_EFUDATA5 0x20 798 #define JZ_EFUDATA6 0x24 799 #define JZ_EFUDATA7 0x28 800 801 #endif /* INGENIC_REGS_H */ 802
Indexes created Sun Aug 09 00:24:28 UTC 2026