| /src/sys/dev/mii/ |
| rgephy.c | 188 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
233 PHY_WRITE(sc, MII_100T2CR, 0);
234 PHY_WRITE(sc, MII_ANAR, anar);
235 PHY_WRITE(sc, MII_BMCR,
249 PHY_WRITE(sc, MII_100T2CR,
252 PHY_WRITE(sc, MII_100T2CR, gig | GTCR_MAN_MS);
253 PHY_WRITE(sc, MII_BMCR,
257 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
459 PHY_WRITE(mii, MII_ANAR, anar);
461 PHY_WRITE(mii, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX)
[all...] |
| brgphy.c | 330 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
364 PHY_WRITE(sc, MII_100T2CR, 0);
365 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
366 PHY_WRITE(sc, MII_BMCR, speed);
373 PHY_WRITE(sc, MII_100T2CR, gig);
374 PHY_WRITE(sc, MII_BMCR,
383 PHY_WRITE(sc, MII_100T2CR, gig);
634 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
644 PHY_WRITE(sc, BRGPHY_5708S_BLOCK_ADDR,
719 PHY_WRITE(sc, BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_GP_STATUS)
[all...] |
| etphy.c | 208 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
219 PHY_WRITE(sc, MII_BMCR, bmcr);
220 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_PDOWN);
234 PHY_WRITE(sc, MII_BMCR, bmcr);
237 PHY_WRITE(sc, MII_BMCR,
279 PHY_WRITE(sc, ETPHY_CTRL, ETPHY_CTRL_DIAG | ETPHY_CTRL_RSV1);
281 PHY_WRITE(sc, ETPHY_INDEX, ETPHY_INDEX_MAGIC);
284 PHY_WRITE(sc, ETPHY_CTRL, ETPHY_CTRL_RSV1);
289 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN | BMCR_S1000);
290 PHY_WRITE(sc, ETPHY_CTRL
[all...] |
| atphy.c | 134 PHY_WRITE(sc, 0x0d, 0x0007);
135 PHY_WRITE(sc, 0x0e, 0x8016);
136 PHY_WRITE(sc, 0x0d, 0x4007);
138 PHY_WRITE(sc, 0x0e, reg | __SHIFTIN(data, __BITS(4, 3)));
239 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
269 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
285 PHY_WRITE(sc, MII_100T2CR, 0);
286 PHY_WRITE(sc, MII_ANAR, anar);
289 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
422 PHY_WRITE(sc, 29, 0x29)
[all...] |
| ipgphy.c | 161 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
197 PHY_WRITE(sc, MII_100T2CR, 0);
198 PHY_WRITE(sc, MII_BMCR, speed);
344 PHY_WRITE(sc, MII_ANAR, reg | ANAR_CSMA);
356 PHY_WRITE(sc, MII_100T2CR, reg);
358 PHY_WRITE(sc, MII_BMCR, BMCR_FDX | BMCR_AUTOEN | BMCR_STARTNEG);
367 PHY_WRITE(sc, 31, 0x0001);
368 PHY_WRITE(sc, 27, 0x01e0);
369 PHY_WRITE(sc, 31, 0x0002);
370 PHY_WRITE(sc, 27, 0xeb8e)
[all...] |
| ikphy.c | 168 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
215 PHY_WRITE(sc, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
226 PHY_WRITE(sc, GG82563_PHY_SPEC_CTRL, phy_data);
234 PHY_WRITE(sc, GG82563_PHY_SPEC_CTRL_2, phy_data);
239 PHY_WRITE(sc, GG82563_PHY_PWR_MGMT_CTRL, phy_data);
243 PHY_WRITE(sc, GG82563_PHY_KMRN_MODE_CTRL, phy_data);
251 PHY_WRITE(sc, GG82563_PHY_INBAND_CTRL, phy_data);
261 PHY_WRITE(sc, MII_BMCR, phy_data | BMCR_STARTNEG);
277 PHY_WRITE(sc, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
352 PHY_WRITE(sc, GG82563_PHY_KMRN_MODE_CTRL, kmrn)
[all...] |
| ciphy.c | 158 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
193 PHY_WRITE(sc, MII_GTCR, 0);
194 PHY_WRITE(sc, MII_BMCR, speed);
195 PHY_WRITE(sc, MII_ANAR, ANAR_CSMA);
200 PHY_WRITE(sc, MII_GTCR, gig);
201 PHY_WRITE(sc, MII_BMCR,
213 PHY_WRITE(sc, MII_GTCR,
216 PHY_WRITE(sc, MII_GTCR, gig | GTCR_MAN_MS);
219 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
373 return PHY_WRITE(sc, y, _tmp | z)
[all...] |
| mcommphy.c | 295 PHY_WRITE(sc, YTPHY_EXT_REG_ADDR, YT8511_CLOCK_GATING_REG);
312 PHY_WRITE(sc, YTPHY_EXT_REG_DATA, data);
314 PHY_WRITE(sc, YTPHY_EXT_REG_ADDR, YT8511_SLEEP_CONTROL1_REG);
319 PHY_WRITE(sc, YTPHY_EXT_REG_DATA, data);
321 PHY_WRITE(sc, YTPHY_EXT_REG_ADDR, oldaddr);
358 PHY_WRITE(sc, YTPHY_EXT_REG_ADDR, YT8521_EXT_CHIP_CONFIG);
366 PHY_WRITE(sc, YTPHY_EXT_REG_DATA, data);
368 PHY_WRITE(sc, YTPHY_EXT_REG_ADDR, YT8521_EXT_RGMII_CONFIG1);
377 PHY_WRITE(sc, YTPHY_EXT_REG_DATA, data);
380 PHY_WRITE(sc, YTPHY_EXT_REG_ADDR, oldaddr)
[all...] |
| igphy.c | 271 PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
272 PHY_WRITE(sc, 0x0000, 0x0140);
279 PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
280 PHY_WRITE(sc, 0x0000, 0x3300);
348 PHY_WRITE(sc, IGPHY_PAGE_SELECT, 0x0000);
374 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
386 PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
389 PHY_WRITE(sc, IGPHY_PORT_CTRL, reg);
523 PHY_WRITE(sc, MII_100T2CR, gtcr);
531 PHY_WRITE(sc, MII_100T2CR, gtcr)
[all...] |
| jmphy.c | 142 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
269 PHY_WRITE(sc, JMPHY_TMCTL, val & ~JMPHY_TMCTL_SLEEP_ENB);
272 PHY_WRITE(sc, MII_BMCR, val | BMCR_RESET);
327 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO | BMCR_PDOWN);
348 PHY_WRITE(sc, MII_100T2CR, gig);
350 PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
351 PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_AUTOEN | BMCR_STARTNEG);
|
| bmtphy.c | 174 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
274 PHY_WRITE(sc, 0x1f, data | 0x0080);
278 PHY_WRITE(sc, MII_BMTPHY_AUX2, data | 0x0020);
282 PHY_WRITE(sc, MII_BMTPHY_INTR, data | 0x0004);
286 PHY_WRITE(sc, 0x1f, data & ~0x0080);
|
| ihphy.c | 156 PHY_WRITE(sc, IHPHY_MII_CFG, reg);
182 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
196 PHY_WRITE(sc, IHPHY_MII_ECR, reg);
295 PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_ISO);
306 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
| miivar.h | 247 #define PHY_WRITE(p, r, v) \
265 if ((rv = PHY_WRITE(sc, MII_MMDACR, (daddr & ~MMDACR_FUNCMASK))) != 0)
269 if ((rv = PHY_WRITE(sc, MII_MMDAADR, regnum)) != 0)
273 rv = PHY_WRITE(sc, MII_MMDACR, daddr);
299 return PHY_WRITE(sc, MII_MMDAADR, val);
|
| igphyreg.h | 183 if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
192 if ((rv = PHY_WRITE(sc, IGPHY_PAGE_SELECT, reg & ~0x1f)) != 0)
195 return PHY_WRITE(sc, reg & 0x1f, val);
|
| /src/sys/arch/arm/samsung/ |
| exynos_usbdrdphy.c | 120 #define PHY_WRITE(sc, reg, val) \
176 PHY_WRITE(sc, PHY_REG0, 0);
182 PHY_WRITE(sc, PHY_PARAM0, val);
184 PHY_WRITE(sc, PHY_RESUME, 0);
190 PHY_WRITE(sc, PHY_LINK_SYSTEM, val);
195 PHY_WRITE(sc, PHY_PARAM1, val);
199 PHY_WRITE(sc, PHY_BATCHG, val);
204 PHY_WRITE(sc, PHY_TEST, val);
206 PHY_WRITE(sc, PHY_UTMI, PHY_UTMI_OTGDISABLE);
217 PHY_WRITE(sc, PHY_CLK_RST, val)
[all...] |
| exynos_usbphy.c | 101 #define PHY_WRITE(sc, reg, val) \
174 PHY_WRITE(sc, USB_PHY_HOST_CTRL0, val);
180 PHY_WRITE(sc, USB_PHY_HOST_CTRL0, val);
196 PHY_WRITE(sc, reg, val);
201 PHY_WRITE(sc, reg, val);
215 PHY_WRITE(sc, USB_PHY_HOST_EHCICTRL, val);
|
| /src/sys/arch/arm/amlogic/ |
| gxlphy.c | 91 PHY_WRITE(sc, TSTCNTL, 0);
92 PHY_WRITE(sc, TSTCNTL, TSTCNTL_TEST_MODE);
93 PHY_WRITE(sc, TSTCNTL, 0);
94 PHY_WRITE(sc, TSTCNTL, TSTCNTL_TEST_MODE);
100 PHY_WRITE(sc, TSTCNTL, 0);
109 PHY_WRITE(sc, TSTCNTL,
123 PHY_WRITE(sc, TSTWRITE, val);
124 PHY_WRITE(sc, TSTCNTL,
212 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
271 PHY_WRITE(sc, MII_BMCR, bmcr)
[all...] |
| mesongxl_usb2phy.c | 68 #define PHY_WRITE(sc, reg, val) \
98 PHY_WRITE(sc, USB2PHY_REG0, val);
105 PHY_WRITE(sc, USB2PHY_REG0, val);
110 PHY_WRITE(sc, USB2PHY_REG0, val);
114 PHY_WRITE(sc, USB2PHY_REG0, val);
125 PHY_WRITE(sc, USB2PHY_REG0, val);
|
| mesongxl_usb3phy.c | 75 #define PHY_WRITE(sc, reg, val) \
108 PHY_WRITE(sc, USB3PHY_REG5, val);
113 PHY_WRITE(sc, USB3PHY_REG0, val);
117 PHY_WRITE(sc, USB3PHY_REG4, val);
123 PHY_WRITE(sc, USB3PHY_REG5, val);
143 PHY_WRITE(sc, USB3PHY_REG1, val);
|
| meson_usbphy.c | 82 #define PHY_WRITE(sc, reg, val) \
142 PHY_WRITE(sc, PREI_USB_PHY_CFG_REG, val);
149 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val);
155 PHY_WRITE(sc, PREI_USB_PHY_CTRL_REG, val);
166 PHY_WRITE(sc, PREI_USB_PHY_ADP_BC_REG, val);
|
| /src/sys/arch/arm/nxp/ |
| imx8mq_usbphy.c | 72 #define PHY_WRITE(sc, reg, val) \
118 PHY_WRITE(sc, PHY_CTL1_ADDR, val);
122 PHY_WRITE(sc, PHY_CTL0_ADDR, val);
126 PHY_WRITE(sc, PHY_CTL2_ADDR, val);
131 PHY_WRITE(sc, PHY_CTL1_ADDR, val);
|
| /src/sys/arch/arm/sunxi/ |
| sunxi_hdmiphy.c | 144 #define PHY_WRITE(sc, reg, val) \
151 PHY_WRITE((sc), (reg), _tval); \
208 PHY_WRITE(sc, ANA_CFG1, 0);
314 PHY_WRITE(sc, ANA_CFG1, ANA_CFG1_LDOEN | ANA_CFG1_ENVBS | ANA_CFG1_ENBI);
315 PHY_WRITE(sc, PLL_CFG1, 0);
332 PHY_WRITE(sc, PLL_CFG1, inittab->pll_cfg1 & ~PLL_CFG1_CKIN_SEL);
333 PHY_WRITE(sc, PLL_CFG2, (inittab->pll_cfg2 & ~PLL_CFG2_PREDIV) | prediv);
335 PHY_WRITE(sc, PLL_CFG3, inittab->pll_cfg3);
355 PHY_WRITE(sc, ANA_CFG1, inittab->ana_cfg1);
356 PHY_WRITE(sc, ANA_CFG2, inittab->ana_cfg2 | rcalib)
[all...] |
| sunxi_usb3phy.c | 93 #define PHY_WRITE(phy, reg, val) \
123 PHY_WRITE(phy, SUNXI_PHY_EXTERNAL_CONTROL, val);
127 PHY_WRITE(phy, SUNXI_PIPE_CLOCK_CONTROL, val);
131 PHY_WRITE(phy, SUNXI_APP, val);
133 PHY_WRITE(phy, SUNXI_PHY_TUNE_LOW, PTL_MAGIC);
144 PHY_WRITE(phy, SUNXI_PHY_TUNE_HIGH, val);
|
| sun9i_a80_usbphy.c | 76 #define PHY_WRITE(sc, reg, val) \
125 PHY_WRITE(sc, PMU_CFG, val);
129 PHY_WRITE(sc, PMU_CFG, val);
|
| /src/sys/dev/ic/ |
| bwi.c | 506 #define RESTORE_PHY_REG(mac, regs, n) PHY_WRITE((mac), 0x##n, (regs)->phy_##n)
1818 PHY_WRITE(mac, 0x28, 0x8018);
1824 PHY_WRITE(mac, 0x47a, 0xc111);
3182 PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);
3183 PHY_WRITE(mac, phy->phy_tbl_data_lo, data);
3194 PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);
3195 PHY_WRITE(mac, phy->phy_tbl_data_hi, data >> 16);
3196 PHY_WRITE(mac, phy->phy_tbl_data_lo, data & 0xffff);
3202 PHY_WRITE(mac, BWI_PHYR_NRSSI_CTRL, ofs);
3203 PHY_WRITE(mac, BWI_PHYR_NRSSI_DATA, (uint16_t)data)
[all...] |
