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    Searched refs:PIPE0_DMIF_BUFFER_CONTROL (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_mem_input.h 185 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\
186 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh)
  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 442 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
sid.h 330 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
evergreend.h 1218 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
radeon_evergreen.c 1875 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1878 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
radeon_si.c 2014 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
2017 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
radeon_cik.c 8920 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
8923 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 638 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
643 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
amdgpu_dce_v11_0.c 664 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
669 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
sid.h 332 #define PIPE0_DMIF_BUFFER_CONTROL 0x0328

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