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    Searched refs:PIPECONF (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
display.c 67 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
82 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
310 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
handlers.c 1987 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1988 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1989 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1990 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
icl_dsi.c 938 tmp = I915_READ(PIPECONF(dsi_trans));
940 I915_WRITE(PIPECONF(dsi_trans), tmp);
943 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
1121 tmp = I915_READ(PIPECONF(dsi_trans));
1123 I915_WRITE(PIPECONF(dsi_trans), tmp);
1126 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
1470 tmp = I915_READ(PIPECONF(dsi_trans));
intel_color.c 453 val = I915_READ(PIPECONF(pipe));
456 I915_WRITE(PIPECONF(pipe), val);
466 val = I915_READ(PIPECONF(pipe));
469 I915_WRITE(PIPECONF(pipe), val);
intel_display.c 1097 i915_reg_t reg = PIPECONF(cpu_transcoder);
1280 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1674 pipeconf_val = I915_READ(PIPECONF(pipe));
1683 * that in pipeconf reg. For HDMI we must use 8bpc
1727 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1873 reg = PIPECONF(cpu_transcoder);
1914 reg = PIPECONF(cpu_transcoder);
5385 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5455 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5481 /* BPC in FDI rx is consistent with that in PIPECONF */
8776 u32 pipeconf; local
    [all...]
intel_crt.c 674 pipeconf_reg = PIPECONF(pipe);
691 u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg); local
694 pipeconf | PIPECONF_FORCE_BORDER);
704 intel_uncore_write(uncore, pipeconf_reg, pipeconf);
intel_display_power.c 1120 if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
1122 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
1136 return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
1137 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
vlv_dsi.c 996 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
intel_dp.c 2357 * some conflicting bits in PIPECONF which will mess up
7050 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_reg.h 5871 #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)

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