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    Searched refs:PIPE_B (Results 1 - 25 of 27) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
handlers.c 1983 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1988 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1993 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1998 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
2003 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
2008 MMIO_D(CURCNTR(PIPE_B), D_ALL);
2012 MMIO_D(CURPOS(PIPE_B), D_ALL);
2016 MMIO_D(CURBASE(PIPE_B), D_ALL);
2020 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL);
2043 MMIO_D(DSPCNTR(PIPE_B), D_ALL)
    [all...]
reg.h 76 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
85 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
display.c 54 pipe = PIPE_B;
401 [PIPE_B] = PIPE_B_VBLANK,
interrupt.c 455 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
cmd_parser.c 1224 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1226 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1282 info->pipe = PIPE_B;
1296 info->pipe = PIPE_B;
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_pci.c 109 [PIPE_B] = CURSOR_B_OFFSET, \
115 [PIPE_B] = CURSOR_B_OFFSET, \
122 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
129 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
166 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
224 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
309 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
360 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
387 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
436 .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
    [all...]
i915_reg.h 8136 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8139 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8142 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8145 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8164 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8167 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8170 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8173 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8189 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8192 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
    [all...]
intel_pm.c 490 case PIPE_B:
969 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
970 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
976 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
1019 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1020 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1031 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1032 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1044 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1045 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI)
    [all...]
intel_device_info.c 931 runtime->num_scalers[PIPE_B] = 2;
954 runtime->num_sprites[PIPE_B] = 2;
995 enabled_mask &= ~BIT(PIPE_B);
i915_irq.c 524 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
1332 case PIPE_B:
1767 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
3525 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3699 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3817 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_dpio_phy.c 802 if (ch == DPIO_CH0 && pipe == PIPE_B)
814 if (pipe != PIPE_B) {
835 if (pipe != PIPE_B)
844 if (pipe != PIPE_B)
857 if (pipe != PIPE_B)
967 if (pipe != PIPE_B) {
intel_pipe_crc.c 187 case PIPE_B:
251 case PIPE_B:
intel_display_power.c 41 return "PIPE_B";
1122 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
1123 i830_enable_pipe(dev_priv, PIPE_B);
1129 i830_disable_pipe(dev_priv, PIPE_B);
1137 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1438 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1562 assert_pll_disabled(dev_priv, PIPE_B);
2861 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3062 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3144 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C)
    [all...]
intel_display.h 108 PIPE_B,
127 TRANSCODER_B = PIPE_B,
vlv_dsi.c 996 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
1020 *pipe = port == PORT_A ? PIPE_A : PIPE_B;
1879 intel_encoder->pipe_mask = BIT(PIPE_B);
intel_sprite.c 1048 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
3087 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
3136 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
icl_dsi.c 767 case PIPE_B:
1457 *pipe = PIPE_B;
intel_display.c 1350 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1368 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B,
1483 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1491 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
5678 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5698 case PIPE_B:
7327 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
7671 case PIPE_B:
7694 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
8245 if (pipe == PIPE_B)
    [all...]
intel_display_types.h 1420 case PIPE_B:
intel_lvds.c 908 intel_encoder->pipe_mask = BIT(PIPE_B);
intel_dp.c 835 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
965 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
3657 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
4263 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
7425 if (pipe != PIPE_A && pipe != PIPE_B)
7428 if (pipe != PIPE_A && pipe != PIPE_B)
7661 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
intel_panel.c 581 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
1759 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
intel_ddi.c 1879 case PIPE_B:
2107 *pipe_mask = BIT(PIPE_B);
  /src/sys/external/bsd/drm/dist/shared-core/
i915_suspend.c 308 i915_save_palette(dev, PIPE_B);
465 i915_restore_palette(dev, PIPE_B);
i915_drv.h 46 PIPE_B,

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