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  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
qcom,mmcc-msm8960.h 128 #define PLL1 117
stm32mp1-clks.h 185 #define PLL1 176
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
ste-nomadik-stn8815.dtsi 196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
219 pll1: pll1@0 { label in label:src
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
230 clocks = <&pll1>;
  /src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/ingenic/
gcw0.dts 445 * Put high-speed peripherals under PLL1, such that we can change the

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