Searched refs:PLL2 (Results 1 - 4 of 4) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h129 #define PLL2 118 macro
H A Dstm32mp13-clks.h22 #define PLL2 7 macro
H A Dstm32mp1-clks.h186 #define PLL2 177 macro
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi196 * that is parent of TIMCLK, PLL1 and PLL2
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */

Completed in 9 milliseconds