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  /src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
qcom,mmcc-msm8960.h 129 #define PLL2 118
stm32mp1-clks.h 186 #define PLL2 177
  /src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
ste-nomadik-stn8815.dtsi 196 * that is parent of TIMCLK, PLL1 and PLL2
241 /* PLL2 is usually 864 MHz and divided into a few fixed rates */
242 pll2: pll2@0 { label in label:src
253 clocks = <&pll2>;
268 clocks = <&pll2>;
276 clocks = <&pll2>;

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