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    Searched refs:PP_ASSERT_WITH_CODE (Results 1 - 25 of 32) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_vega20_smumgr.c 174 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
176 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
178 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
181 PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
186 PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
191 PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr,
218 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
220 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
222 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
230 PP_ASSERT_WITH_CODE((ret = vega20_send_msg_to_smc_with_parameter(hwmgr
    [all...]
amdgpu_vega12_smumgr.c 52 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
54 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
56 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
58 PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
62 PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
67 PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr,
94 PP_ASSERT_WITH_CODE(table_id < TABLE_COUNT,
96 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
98 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
106 PP_ASSERT_WITH_CODE(smu9_send_msg_to_smc_with_parameter(hwmgr
    [all...]
amdgpu_smu7_smumgr.c 45 PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL);
46 PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL);
62 PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL);
63 PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL);
99 PP_ASSERT_WITH_CODE((0 == (3 & smc_start_address)), "SMC address must be 4 byte aligned.", return -EINVAL);
100 PP_ASSERT_WITH_CODE((limit > (smc_start_address + byte_count)), "SMC address is beyond the SMC RAM area.", return -EINVAL);
397 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
400 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
403 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr,
406 PP_ASSERT_WITH_CODE(0 == smu7_populate_single_firmware_entry(hwmgr
    [all...]
amdgpu_iceland_smumgr.c 169 PP_ASSERT_WITH_CODE((limit >= byte_count), "SMC address is beyond the SMC RAM area.", return -EINVAL);
183 PP_ASSERT_WITH_CODE((0 == byte_count), "SMC size must be divisible by 4.", return -EINVAL);
350 PP_ASSERT_WITH_CODE(false,
401 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
403 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
405 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
414 PP_ASSERT_WITH_CODE(false, "Iceland should always support EVV", return -EINVAL);
427 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
451 PP_ASSERT_WITH_CODE(false,
457 PP_ASSERT_WITH_CODE(false
    [all...]
amdgpu_fiji_smumgr.c 156 PP_ASSERT_WITH_CODE(false,
235 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
250 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_addr,
258 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, level_addr,
271 PP_ASSERT_WITH_CODE(0 == fiji_setup_graphics_level_structure(hwmgr),
275 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
279 PP_ASSERT_WITH_CODE(0 == fiji_start_avfs_btc(hwmgr),
514 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
620 PP_ASSERT_WITH_CODE(false,
707 PP_ASSERT_WITH_CODE(false
    [all...]
amdgpu_vegam_smumgr.c 144 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
216 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
799 PP_ASSERT_WITH_CODE((clock >= min),
829 PP_ASSERT_WITH_CODE((0 == result),
920 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
970 PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
997 PP_ASSERT_WITH_CODE(!result,
1003 PP_ASSERT_WITH_CODE(!result,
1052 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1103 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count
    [all...]
amdgpu_smu10_smumgr.c 128 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
130 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
132 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
160 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
162 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
164 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
amdgpu_vega10_smumgr.c 49 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
51 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
53 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
86 PP_ASSERT_WITH_CODE(table_id < MAX_SMU_TABLE,
88 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].version != 0,
90 PP_ASSERT_WITH_CODE(priv->smu_tables.entry[table_id].size != 0,
175 PP_ASSERT_WITH_CODE(!smu9_send_msg_to_smc(hwmgr,
354 PP_ASSERT_WITH_CODE(!vega10_verify_smc_interface(hwmgr),
amdgpu_tonga_smumgr.c 457 PP_ASSERT_WITH_CODE(!result,
462 PP_ASSERT_WITH_CODE(!result,
467 PP_ASSERT_WITH_CODE(!result,
472 PP_ASSERT_WITH_CODE(!result,
477 PP_ASSERT_WITH_CODE(!result,
561 PP_ASSERT_WITH_CODE(result == 0,
643 PP_ASSERT_WITH_CODE((!result),
741 PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
817 PP_ASSERT_WITH_CODE(
992 PP_ASSERT_WITH_CODE(
    [all...]
amdgpu_polaris10_smumgr.c 135 PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
146 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
153 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
161 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
170 PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
186 PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
192 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
197 PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
243 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
313 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result)
    [all...]
amdgpu_ci_smumgr.c 318 PP_ASSERT_WITH_CODE(result == 0,
555 PP_ASSERT_WITH_CODE(false,
588 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.cac_leakage_table,
590 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count <= 8,
592 PP_ASSERT_WITH_CODE(hwmgr->dyn_state.cac_leakage_table->count == hwmgr->dyn_state.vddc_dependency_on_sclk->count,
616 PP_ASSERT_WITH_CODE(data->vddc_voltage_table.count <= 8,
776 PP_ASSERT_WITH_CODE(NULL != hwmgr->dyn_state.vddc_dependency_on_sclk,
856 PP_ASSERT_WITH_CODE(0 == result, "do not populate SMC VDDC voltage table", return -EINVAL);
886 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC VDDCI voltage table", return -EINVAL);
914 PP_ASSERT_WITH_CODE(result == 0, "do not populate SMC mvdd voltage table", return -EINVAL)
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
pp_debug.h 39 #define PP_ASSERT_WITH_CODE(cond, msg, code) \
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_vega12_hwmgr.c 464 PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
494 PP_ASSERT_WITH_CODE(!ret,
499 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
513 PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
530 PP_ASSERT_WITH_CODE(!ret,
538 PP_ASSERT_WITH_CODE(!ret,
570 PP_ASSERT_WITH_CODE(!ret,
583 PP_ASSERT_WITH_CODE(!ret,
596 PP_ASSERT_WITH_CODE(!ret,
609 PP_ASSERT_WITH_CODE(!ret
    [all...]
amdgpu_vega20_hwmgr.c 499 PP_ASSERT_WITH_CODE(!ret,
537 PP_ASSERT_WITH_CODE(!ret,
542 PP_ASSERT_WITH_CODE(*num_of_levels > 0,
557 PP_ASSERT_WITH_CODE(!ret,
562 PP_ASSERT_WITH_CODE(*clk,
576 PP_ASSERT_WITH_CODE(!ret,
584 PP_ASSERT_WITH_CODE(!ret,
604 PP_ASSERT_WITH_CODE(!ret,
625 PP_ASSERT_WITH_CODE(!ret,
657 PP_ASSERT_WITH_CODE(!ret
    [all...]
amdgpu_vega12_thermal.c 39 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc(hwmgr,
80 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(
98 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(
115 PP_ASSERT_WITH_CODE(
129 PP_ASSERT_WITH_CODE(!vega12_disable_fan_control_feature(hwmgr),
amdgpu_process_pptables_v1_0.c 62 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE16____),
64 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE64____),
66 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE512____),
68 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE1024____),
70 PP_ASSERT_WITH_CODE((~powerplay_caps & ____RETIRE2048____),
170 PP_ASSERT_WITH_CODE((0 != vddc_lookup_pp_tables->ucNumEntries),
330 PP_ASSERT_WITH_CODE((0 != clk_volt_pp_table->count),
360 PP_ASSERT_WITH_CODE((0 != limitable->ucNumEntries), "Invalid PowerPlay Table!", return -1);
383 PP_ASSERT_WITH_CODE((0 != mclk_dep_table->ucNumEntries),
430 PP_ASSERT_WITH_CODE((0 != tonga_table->ucNumEntries)
    [all...]
amdgpu_vega12_processpptables.c 73 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
76 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
111 PP_ASSERT_WITH_CODE(
277 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL),
281 PP_ASSERT_WITH_CODE((powerplay_table != NULL),
285 PP_ASSERT_WITH_CODE((result == 0),
290 PP_ASSERT_WITH_CODE((result == 0),
294 PP_ASSERT_WITH_CODE((result == 0),
372 PP_ASSERT_WITH_CODE(pp_table, "Missing PowerPlay Table!",
382 PP_ASSERT_WITH_CODE(pp_table->usStateArrayOffset > 0
    [all...]
amdgpu_vega10_hwmgr.c 103 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
113 PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
531 PP_ASSERT_WITH_CODE(lookup_table->count != 0,
542 PP_ASSERT_WITH_CODE(entry_id < table_info->vdd_dep_on_socclk->count,
586 PP_ASSERT_WITH_CODE(!atomctrl_get_voltage_evv_on_sclk_ai(hwmgr,
593 PP_ASSERT_WITH_CODE((vddc < 2000 && vddc != 0),
723 PP_ASSERT_WITH_CODE(lookup_table && lookup_table->count,
782 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
784 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
787 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table
    [all...]
amdgpu_vega10_processpptables.c 81 PP_ASSERT_WITH_CODE((powerplay_table->sHeader.format_revision >=
84 PP_ASSERT_WITH_CODE(powerplay_table->usStateArrayOffset,
86 PP_ASSERT_WITH_CODE(powerplay_table->sHeader.structuresize > 0,
88 PP_ASSERT_WITH_CODE(state_arrays->ucNumEntries > 0,
138 PP_ASSERT_WITH_CODE((powerplay_table->usThermalControllerOffset != 0),
176 PP_ASSERT_WITH_CODE((fan_table_v1->ucRevId >= 8),
356 PP_ASSERT_WITH_CODE((mm_dependency_table->ucNumEntries != 0),
582 PP_ASSERT_WITH_CODE(clk_dep_table->ucNumEntries,
616 PP_ASSERT_WITH_CODE(mclk_dep_table->ucNumEntries,
657 PP_ASSERT_WITH_CODE((clk_dep_table->ucNumEntries != 0)
    [all...]
amdgpu_smu7_hwmgr.c 124 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
134 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic),
175 PP_ASSERT_WITH_CODE((7 >= link_width),
236 PP_ASSERT_WITH_CODE((NULL != voltage_table),
271 PP_ASSERT_WITH_CODE((0 == result),
282 PP_ASSERT_WITH_CODE((0 == result),
291 PP_ASSERT_WITH_CODE((0 == result),
301 PP_ASSERT_WITH_CODE((0 == result),
310 PP_ASSERT_WITH_CODE((0 == result),
319 PP_ASSERT_WITH_CODE((0 == result)
    [all...]
amdgpu_smu_helper.c 215 PP_ASSERT_WITH_CODE((NULL != vol_table),
258 PP_ASSERT_WITH_CODE((0 != dep_table->count),
261 PP_ASSERT_WITH_CODE((NULL != vol_table),
274 PP_ASSERT_WITH_CODE((0 == result),
286 PP_ASSERT_WITH_CODE((0 != dep_table->count),
289 PP_ASSERT_WITH_CODE((NULL != vol_table),
302 PP_ASSERT_WITH_CODE((0 == result),
313 PP_ASSERT_WITH_CODE((0 != lookup_table->count),
316 PP_ASSERT_WITH_CODE((NULL != vol_table),
399 PP_ASSERT_WITH_CODE((NULL != lookup_table)
    [all...]
amdgpu_vega10_thermal.c 193 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
210 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
227 PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
243 PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
440 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
471 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
amdgpu_vega20_thermal.c 47 PP_ASSERT_WITH_CODE(!ret,
76 PP_ASSERT_WITH_CODE(!ret,
113 PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
amdgpu_vega10_powertune.c 808 PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);
1191 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);
1208 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);
1212 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);
1216 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);
1222 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);
1226 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);
1235 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
1255 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);
1259 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result)
    [all...]
amdgpu_hardwaremanager.c 391 PP_ASSERT_WITH_CODE((NULL != state), "Invalid Input!", return -EINVAL);
392 PP_ASSERT_WITH_CODE((NULL != pclock_info), "Invalid Input!", return -EINVAL);
396 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve minimum clocks.", return result);
407 PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve maximum clocks.", return result);

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