HomeSort by: relevance | last modified time | path
    Searched refs:PP_HOST_TO_SMC_UL (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
pp_endian.h 29 #define PP_HOST_TO_SMC_UL(X) cpu_to_be32(X)
35 #define CONVERT_FROM_HOST_TO_SMC_UL(X) ((X) = PP_HOST_TO_SMC_UL(X))
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_iceland_smumgr.c 787 PP_HOST_TO_SMC_UL(5);
789 PP_HOST_TO_SMC_UL(30);
949 graphic_level->MinVddc = PP_HOST_TO_SMC_UL(graphic_level->MinVddc * VOLTAGE_SCALE);
1329 memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
1331 memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
1332 memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
1446 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1448 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1504 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE);
1506 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->min_vddci_in_pptable * VOLTAGE_SCALE)
    [all...]
amdgpu_vegam_smumgr.c 473 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
590 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
591 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1176 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1270 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1271 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1272 arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time);
1273 arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate);
1274 arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3);
1588 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0)
    [all...]
amdgpu_ci_smumgr.c 460 level->MinVddc = PP_HOST_TO_SMC_UL(level->MinVddc * VOLTAGE_SCALE);
749 dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bapm_temp_gradient);
1014 table->LinkLevel[i].DownT = PP_HOST_TO_SMC_UL(5);
1015 table->LinkLevel[i].UpT = PP_HOST_TO_SMC_UL(30);
1281 memory_level->MinVddc = PP_HOST_TO_SMC_UL(memory_level->MinVddc * VOLTAGE_SCALE);
1283 memory_level->MinVddci = PP_HOST_TO_SMC_UL(memory_level->MinVddci * VOLTAGE_SCALE);
1284 memory_level->MinMvdd = PP_HOST_TO_SMC_UL(memory_level->MinMvdd * VOLTAGE_SCALE);
1398 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE);
1400 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE);
1456 table->MemoryACPILevel.MinVddci = PP_HOST_TO_SMC_UL(data->acpi_vddci * VOLTAGE_SCALE)
    [all...]
amdgpu_polaris10_smumgr.c 672 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
788 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
789 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1271 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1360 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1361 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1723 table->BTCGB_VDROOP_TABLE[0].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1724 table->BTCGB_VDROOP_TABLE[0].a1 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1725 table->BTCGB_VDROOP_TABLE[0].a2 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1726 table->BTCGB_VDROOP_TABLE[1].a0 = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0)
    [all...]
amdgpu_tonga_smumgr.c 530 PP_HOST_TO_SMC_UL(5);
532 PP_HOST_TO_SMC_UL(30);
1253 PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
1276 PP_HOST_TO_SMC_UL(dll_cntl);
1278 PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
1280 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
1282 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
1284 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
1286 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
1288 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2)
    [all...]
amdgpu_fiji_smumgr.c 850 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
851 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
1408 PP_HOST_TO_SMC_UL(us_mvdd * VOLTAGE_SCALE);
1522 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1523 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
2098 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2586 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2588 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2600 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2603 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp))
    [all...]

Completed in 43 milliseconds