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    Searched refs:PSR_MODE (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/arch/arm/arm32/
setstack.S 64 bic r2, r3, #(PSR_MODE)
84 bic r2, r3, #(PSR_MODE)
locore.S 157 bic r2, r2, #(PSR_MODE)
fault.c 377 if (__predict_false((tf->tf_spsr & PSR_MODE)==PSR_UND32_MODE)) {
676 (tf->tf_spsr & PSR_MODE) == PSR_ABT32_MODE) {
683 tf->tf_spsr &= ~PSR_MODE;
  /src/sys/arch/arm/arm/
fiq_subr.S 51 bic r2, r2, #(PSR_MODE) ; \
undefined.c 316 if ((tf->tf_spsr & PSR_MODE) != PSR_USR32_MODE) {
341 if ((tf->tf_spsr & PSR_MODE) == PSR_USR32_MODE) {
cpufunc.c 2047 if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
2124 (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE)
2138 if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
2187 if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
2243 (frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE)
2314 if ((frame->tf_spsr & PSR_MODE) == PSR_SVC32_MODE) {
armv6_start.S 632 and r0, r0, #(PSR_MODE) /* Mode is in the low 5 bits of CPSR */
646 bic r0, r0, #(PSR_MODE)
  /src/sys/arch/arm/include/
frame.h 82 #define TRAP_USERMODE(tf) (((tf)->tf_spsr & PSR_MODE) == PSR_USR32_MODE)
locore.h 124 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & I32_bit) == 0)
127 (((psr) & PSR_MODE) == PSR_USR32_MODE && ((psr) & IF32_bits) == 0)
cpu.h 119 #define CLKF_USERMODE(cf) (((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_USR32_MODE)
129 ((cf)->cf_tf.tf_spsr & PSR_MODE) == PSR_UND32_MODE)
armreg.h 84 #define PSR_MODE 0x0000001f /* mode mask */
  /src/sys/arch/arm/include/arm32/
frame.h 189 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
231 and r7, r0, #(PSR_MODE) /* Test for USR32 mode */ ;\
282 and r0, r0, #(PSR_MODE) /* check for SVC32 mode */ ;\
428 bic tmp, tmp, #(PSR_MODE); /* Fix for SVC mode */ \
442 and r2, r3, #(PSR_MODE); \
  /src/sys/arch/arm/ofw/
ofw_irq.S 377 /*assert((cpsr & PSR_MODE) == PSR_IRQ32_MODE);*/
449 bic r3, r3, #(PSR_MODE)
454 bic r3, r3, #(PSR_MODE)
  /src/sys/arch/hpcarm/hpcarm/
locore.S 59 bic r4, r4, #(PSR_MODE)
197 bic r2, r2, #(PSR_MODE)
  /src/sys/arch/evbarm/stand/board/
s3c2410_vector.S 67 bic r0, r0, #PSR_MODE
s3c2800_vector.S 99 bic r0, r0, #PSR_MODE
  /src/sys/arch/acorn32/stand/boot32/
start.S 236 bic r6, r6, #PSR_MODE /* clear processor mode */
  /src/sys/arch/evbarm/gemini/
gemini_start.S 126 bic r0, r0, #PSR_MODE

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