| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiBaseInfo.h | 97 case Lanai::R24:
|
| /src/external/bsd/pcc/dist/pcc/arch/powerpc/ |
| macdefs.h | 171 #define R24 24
258 SAREG, /* R24 */ \
325 { R22, R23, -1 }, { R24, R25, -1 }, \
|
| /src/external/gpl3/gcc/dist/libgcc/config/avr/ |
| lib1funcs.S | 222 #define r_arg1 r24 /* multiplier */
263 ;;; R25:R24 = (unsigned int) R22 * (unsigned int) R24
274 ;;; R25:R24 = (signed int) R22 * (signed int) R24
308 ;;; R25:R24 = R23:R22 * R25:R24
709 ;; R24:R22 *= R20:R18
742 ;; R24:R22 *= R20:R18
1107 #define A2 r24
[all...] |
| /src/external/gpl3/gcc.old/dist/libgcc/config/avr/ |
| lib1funcs.S | 217 #define r_arg1 r24 /* multiplier */
258 ;;; R25:R24 = (unsigned int) R22 * (unsigned int) R24
269 ;;; R25:R24 = (signed int) R22 * (signed int) R24
303 ;;; R25:R24 = R23:R22 * R25:R24
704 ;; R24:R22 *= R20:R18
737 ;; R24:R22 *= R20:R18
1102 #define A2 r24
[all...] |
| /src/external/gpl3/gcc/dist/libgcc/config/avr/libf7/ |
| asm-defs.h | 93 to move R25:R24 to R31:R30, i.e. plain register numbers
107 r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, \
123 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, \
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/avr/libf7/ |
| asm-defs.h | 93 to move R25:R24 to R31:R30, i.e. plain register numbers
107 r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, \
123 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, \
|
| /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_onetimeauth/poly1305/sse2/ |
| poly1305_sse2.c | 211 xmmi R20, R21, R22, R23, R24, S21, S22, S23, S24;
257 R24 = _mm_unpacklo_epi64(T1, T3);
265 R24 = T1;
279 R24 = _mm_shuffle_epi32(T1, _MM_SHUFFLE(0, 0, 0, 0));
284 S24 = _mm_mul_epu32(R24, FIVE);
494 v44 = _mm_mul_epu32(v44, R24);
616 v44 = _mm_mul_epu32(v44, R24);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 123 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
132 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
|
| HexagonFrameLowering.h | 97 { Hexagon::R25, -36 }, { Hexagon::R24, -40 }, { Hexagon::D12, -40 },
|
| HexagonFrameLowering.cpp | 1078 Hexagon::R25, Hexagon::R24, Hexagon::R27, Hexagon::R26,
|
| HexagonISelLowering.cpp | 293 .Case("r24", Hexagon::R24)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/Disassembler/ |
| LanaiDisassembler.cpp | 160 Lanai::R24, Lanai::R25, Lanai::R26, Lanai::R27, Lanai::R28, Lanai::R29,
|
| /src/external/gpl3/gdb.old/dist/sim/aarch64/ |
| cpustate.h | 66 R24,
|
| /src/external/gpl3/gdb/dist/sim/aarch64/ |
| cpustate.h | 66 R24,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/Disassembler/ |
| ARCDisassembler.cpp | 117 ARC::R21, ARC::R22, ARC::R23, ARC::R24, ARC::R25, ARC::GP, ARC::FP,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/Disassembler/ |
| AVRDisassembler.cpp | 67 AVR::R24, AVR::R25, AVR::R26, AVR::R27,
211 unsigned d = fieldFromInstruction(Insn, 4, 2) * 2 + 24; // starts at r24:r25
|
| /src/sys/external/bsd/gnu-efi/dist/inc/ |
| efidebug.h | 352 UINT64 R24;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 552 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| AVRISelLowering.cpp | 992 AVR::R25, AVR::R24, AVR::R23, AVR::R22, AVR::R21, AVR::R20,
1944 case 'w': // Special upper register pairs: r24, r26, r28, r30.
2085 .Case("r24", AVR::R24).Case("r25", AVR::R25).Case("r26", AVR::R26)
2098 .Case("r24", AVR::R25R24).Case("r26", AVR::R27R26)
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 126 {PPC::R24, -32}, \
|
