Searched refs:R9A07G054_CLK_P0_DIV2 (Results 1 - 2 of 2) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dr9a07g054-cpg.h35 #define R9A07G054_CLK_P0_DIV2 22 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/renesas/
H A Dr9a07g054.dtsi520 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
523 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;

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