| /src/external/gpl3/gcc/dist/libgcc/config/mips/ |
| crtn.S | 31 #define RA $7
33 #define RA $31
39 ld RA,40($sp)
42 lw RA,20($sp)
45 j RA
50 ld RA,40($sp)
53 lw RA,20($sp)
56 j RA
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/mips/ |
| crtn.S | 31 #define RA $7
33 #define RA $31
39 ld RA,40($sp)
42 lw RA,20($sp)
45 j RA
50 ld RA,40($sp)
53 lw RA,20($sp)
56 j RA
|
| /src/external/gpl3/gdb/dist/sim/ppc/ |
| dc-test.01 | 22 11:15:11:15:0:RA: 1:0xfc000000:0x38000000:2
23 11:15:11:15:0:RA: 1:0xfc000000:0x3c000000:2
|
| dc-test.02 | 22 11:15:11:15:0:RA: 1:0xfc000000:0x38000000:2
23 11:15:11:15:0:RA: 1:0xfc000000:0x3c000000:2
|
| dc-complex | 26 ## Expand RA on equality with 0 in Add instructions were if(RA==0) appears.
29 array,boolean: 11:15:11:15:RA: 0xfc000000:0x38000000:0
31 array,boolean: 11:15:11:15:RA: 0xfc000000:0x3c000000:0
36 #array,boolean: 11:15:11:15:RA: 0xfc000000:0x98000000:0
38 #array,boolean: 11:15:11:15:RA: 0xfc000000:0x90000000:0
40 #array,boolean: 11:15:11:15:RA: 0xfc000000:0x80000000:0
|
| powerpc.igen | 36 :cache::::RA:RA:
37 :cache:::signed_word *:rA:RA:(cpu_registers(processor)->gpr + RA)
38 :cache:::uint32_t:RA_BITMASK:RA:(1 << RA)
39 :compute:::int:RA_is_0:RA:(RA == 0)
1724 0.34,6.RT,11.RA,16.D:D:::Load Byte and Zer
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/ppc/ |
| dc-test.01 | 22 11:15:11:15:0:RA: 1:0xfc000000:0x38000000:2
23 11:15:11:15:0:RA: 1:0xfc000000:0x3c000000:2
|
| dc-test.02 | 22 11:15:11:15:0:RA: 1:0xfc000000:0x38000000:2
23 11:15:11:15:0:RA: 1:0xfc000000:0x3c000000:2
|
| dc-complex | 26 ## Expand RA on equality with 0 in Add instructions were if(RA==0) appears.
29 array,boolean: 11:15:11:15:RA: 0xfc000000:0x38000000:0
31 array,boolean: 11:15:11:15:RA: 0xfc000000:0x3c000000:0
36 #array,boolean: 11:15:11:15:RA: 0xfc000000:0x98000000:0
38 #array,boolean: 11:15:11:15:RA: 0xfc000000:0x90000000:0
40 #array,boolean: 11:15:11:15:RA: 0xfc000000:0x80000000:0
|
| powerpc.igen | 36 :cache::::RA:RA:
37 :cache:::signed_word *:rA:RA:(cpu_registers(processor)->gpr + RA)
38 :cache:::uint32_t:RA_BITMASK:RA:(1 << RA)
39 :compute:::int:RA_is_0:RA:(RA == 0)
1724 0.34,6.RT,11.RA,16.D:D:::Load Byte and Zer
[all...] |
| /src/external/gpl3/gdb.old/dist/sim/microblaze/ |
| microblaze.isa | 31 CARRY = C_calc(RA, RB, 0);
32 RD = RA + RB;
39 CARRY = C_calc(RB, ~RA, 1);
40 RD = RB + ~RA + 1;
47 CARRY = C_calc(RA, RB, C_rd);
48 RD = RA + RB + C_rd;
55 CARRY = C_calc(RB, ~RA, C_rd);
56 RD = RB + ~RA + C_rd;
63 RD = RA + RB;
69 RD = RB + ~RA + 1
[all...] |
| /src/external/gpl3/gdb/dist/sim/microblaze/ |
| microblaze.isa | 31 CARRY = C_calc(RA, RB, 0);
32 RD = RA + RB;
39 CARRY = C_calc(RB, ~RA, 1);
40 RD = RB + ~RA + 1;
47 CARRY = C_calc(RA, RB, C_rd);
48 RD = RA + RB + C_rd;
55 CARRY = C_calc(RB, ~RA, C_rd);
56 RD = RB + ~RA + C_rd;
63 RD = RA + RB;
69 RD = RB + ~RA + 1
[all...] |
| /src/external/gpl3/binutils/dist/opcodes/ |
| ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
741 between R's value and the RA value (ie, they cannot both be non zero). */
750 int64_t ra = (insn >> 16) & 0x1f; local
751 if (ra != 0 && value != 0)
771 int64_t ra = (insn >> 16) & 0x1f;
773 if (ra != 0 && pcrel != 0)
1546 /* The RA field in a D or X form instruction which is an updating
1547 load, which means that the RA field may not be zero and may not
1575 /* The RA field in an lmw instruction, which has special value
1602 /* The RA field in the DQ form lq or an lswx instruction, which have specia
[all...] |
| or1k-opc.c | 319 /* l.mfspr $rD,$rA,${uimm16} */
322 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM16), 0 } },
325 /* l.mtspr $rA,$rB,${uimm16-split} */
328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
331 /* l.lwz $rD,${simm16}($rA) */
334 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
337 /* l.lws $rD,${simm16}($rA) */
340 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
343 /* l.lwa $rD,${simm16}($rA) */
346 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }
[all...] |
| /src/external/gpl3/binutils.old/dist/opcodes/ |
| ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
741 between R's value and the RA value (ie, they cannot both be non zero). */
750 int64_t ra = (insn >> 16) & 0x1f; local
751 if (ra != 0 && value != 0)
771 int64_t ra = (insn >> 16) & 0x1f;
773 if (ra != 0 && pcrel != 0)
1546 /* The RA field in a D or X form instruction which is an updating
1547 load, which means that the RA field may not be zero and may not
1575 /* The RA field in an lmw instruction, which has special value
1602 /* The RA field in the DQ form lq or an lswx instruction, which have specia
[all...] |
| or1k-opc.c | 319 /* l.mfspr $rD,$rA,${uimm16} */
322 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM16), 0 } },
325 /* l.mtspr $rA,$rB,${uimm16-split} */
328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
331 /* l.lwz $rD,${simm16}($rA) */
334 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
337 /* l.lws $rD,${simm16}($rA) */
340 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
343 /* l.lwa $rD,${simm16}($rA) */
346 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }
[all...] |
| /src/external/gpl3/gdb.old/dist/opcodes/ |
| ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
695 between R's value and the RA value (ie, they cannot both be non zero). */
704 int64_t ra = (insn >> 16) & 0x1f; local
705 if (ra != 0 && value != 0)
725 int64_t ra = (insn >> 16) & 0x1f;
727 if (ra != 0 && pcrel != 0)
1500 /* The RA field in a D or X form instruction which is an updating
1501 load, which means that the RA field may not be zero and may not
1529 /* The RA field in an lmw instruction, which has special value
1556 /* The RA field in the DQ form lq or an lswx instruction, which have specia
[all...] |
| or1k-opc.c | 319 /* l.mfspr $rD,$rA,${uimm16} */
322 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM16), 0 } },
325 /* l.mtspr $rA,$rB,${uimm16-split} */
328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
331 /* l.lwz $rD,${simm16}($rA) */
334 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
337 /* l.lws $rD,${simm16}($rA) */
340 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
343 /* l.lwa $rD,${simm16}($rA) */
346 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }
[all...] |
| /src/external/gpl3/gdb/dist/opcodes/ |
| ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or
741 between R's value and the RA value (ie, they cannot both be non zero). */
750 int64_t ra = (insn >> 16) & 0x1f; local
751 if (ra != 0 && value != 0)
771 int64_t ra = (insn >> 16) & 0x1f;
773 if (ra != 0 && pcrel != 0)
1546 /* The RA field in a D or X form instruction which is an updating
1547 load, which means that the RA field may not be zero and may not
1575 /* The RA field in an lmw instruction, which has special value
1602 /* The RA field in the DQ form lq or an lswx instruction, which have specia
[all...] |
| or1k-opc.c | 319 /* l.mfspr $rD,$rA,${uimm16} */
322 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (UIMM16), 0 } },
325 /* l.mtspr $rA,$rB,${uimm16-split} */
328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
331 /* l.lwz $rD,${simm16}($rA) */
334 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
337 /* l.lws $rD,${simm16}($rA) */
340 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
343 /* l.lwa $rD,${simm16}($rA) */
346 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| RDFDeadCode.cpp | 88 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)) {
89 if (!LiveNodes.count(RA.Id))
90 WorkQ.push_back(RA.Id);
135 auto RA = DFG.addr<RefNode*>(N);
136 if (DFG.IsDef(RA))
137 processDef(RA, WorkQ);
139 processUse(RA, WorkQ);
145 auto RA = DFG.addr<RefNode*>(N);
146 dbgs() << PrintNode<RefNode*>(RA, DFG) << "\n";
159 for (NodeAddr<RefNode*> RA : IA.Addr->members(DFG)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| TargetSubtargetInfo.cpp | 21 const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
23 : MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
|
| /src/lib/csu/arch/mips/ |
| crti.S | 40 NESTED_NOPROFILE(_init, CALLFRAME_SIZ, ra)
43 REG_S ra, CALLFRAME_RA(sp) # save RA
53 NESTED_NOPROFILE(_fini, CALLFRAME_SIZ, ra)
56 REG_S ra, CALLFRAME_RA(sp) # save RA
|
| /src/sys/external/bsd/gnu-efi/dist/inc/mips64el/ |
| efisetjmp_arch.h | 10 UINT64 RA;
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/IPO/ |
| DeadArgumentElimination.h | 131 bool IsLive(const RetOrArg &RA);
132 void MarkValue(const RetOrArg &RA, Liveness L,
134 void MarkLive(const RetOrArg &RA);
136 void PropagateLiveness(const RetOrArg &RA);
|
