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    Searched refs:RCS0 (Results 1 - 21 of 21) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
mmio_context.c 51 {RCS0, GFX_MODE_GEN7, 0xffff, false}, /* 0x229c */
52 {RCS0, GEN9_CTX_PREEMPT_REG, 0x0, false}, /* 0x2248 */
53 {RCS0, HWSTAM, 0x0, false}, /* 0x2098 */
54 {RCS0, INSTPM, 0xffff, true}, /* 0x20c0 */
55 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 0), 0, false}, /* 0x24d0 */
56 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 1), 0, false}, /* 0x24d4 */
57 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 2), 0, false}, /* 0x24d8 */
58 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 3), 0, false}, /* 0x24dc */
59 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 4), 0, false}, /* 0x24e0 */
60 {RCS0, RING_FORCE_TO_NONPRIV(RENDER_RING_BASE, 5), 0, false}, /* 0x24e4 *
    [all...]
scheduler.c 106 if (workload->ring_id != RCS0)
162 if (ring_id == RCS0) {
190 if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS0)
436 if (workload->ring_id == RCS0 && workload->wa_ctx.indirect_ctx.size) {
826 if (IS_BROADWELL(gvt->dev_priv) && rq->engine->id == RCS0)
1536 if (ring_id == RCS0) {
execlist.c 55 [RCS0] = RCS_AS_CONTEXT_SWITCH,
cmd_parser.c 417 #define R_RCS BIT(RCS0)
587 [RCS0] = {
987 if (IS_BROADWELL(gvt->dev_priv) && s->ring_id != RCS0) {
1088 [RCS0] = {
handlers.c 331 engine_mask |= BIT(RCS0);
1779 id = RCS0;
  /src/sys/external/bsd/drm2/dist/drm/i915/selftests/
mock_gem_device.c 187 i915->engine[RCS0] = mock_engine(i915, "mock", RCS0);
188 if (!i915->engine[RCS0])
191 if (mock_engine_init(i915->engine[RCS0]))
i915_request.c 66 request = mock_request(i915->engine[RCS0]->kernel_context, HZ / 10);
84 request = mock_request(i915->engine[RCS0]->kernel_context, T);
153 request = mock_request(i915->engine[RCS0]->kernel_context, T);
205 ce = i915_gem_context_get_engine(ctx[0], RCS0);
219 ce = i915_gem_context_get_engine(ctx[1], RCS0);
428 .engine = i915->engine[RCS0],
  /src/sys/external/bsd/drm2/dist/drm/i915/
i915_pci.c 174 .engine_mask = BIT(RCS0), \
192 .engine_mask = BIT(RCS0), \
227 .engine_mask = BIT(RCS0), \
313 .engine_mask = BIT(RCS0), \
344 .engine_mask = BIT(RCS0) | BIT(VCS0),
354 .engine_mask = BIT(RCS0) | BIT(VCS0),
362 .engine_mask = BIT(RCS0) | BIT(VCS0), \
390 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
439 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
506 .engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0)
    [all...]
i915_irq.c 3637 intel_engine_signal_breadcrumbs(dev_priv->engine[RCS0]);
3742 intel_engine_signal_breadcrumbs(dev_priv->engine[RCS0]);
3884 intel_engine_signal_breadcrumbs(dev_priv->engine[RCS0]);
i915_gpu_error.c 1168 case RCS0:
  /src/sys/external/bsd/drm2/dist/drm/i915/gt/
intel_engine_cs.c 77 [RCS0] = {
989 if (engine->id != RCS0)
1007 if (engine->id != RCS0)
1023 if (engine->id == RCS0)
intel_engine_types.h 113 RCS0 = 0,
intel_engine_user.c 211 [RENDER_CLASS] = { RCS0, 1 },
intel_mocs.c 361 [RCS0] = __GEN9_RCS0_MOCS0,
selftest_hangcheck.c 1031 struct intel_engine_cs *engine = gt->engine[RCS0];
1158 struct intel_engine_cs *engine = gt->engine[RCS0];
1503 struct intel_engine_cs *engine = gt->engine[RCS0];
intel_reset.c 321 [RCS0] = GEN6_GRDOM_RENDER,
452 [RCS0] = GEN11_GRDOM_RENDER,
intel_ring_submission.c 559 case RCS0:
1610 GEM_BUG_ON(rq->engine->id != RCS0);
intel_lrc.c 4356 [RCS0] = GEN8_RCS_IRQ_SHIFT,
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/
i915_gem_execbuffer.c 1964 if (!IS_GEN(rq->i915, 7) || rq->engine->id != RCS0) {
2282 [I915_EXEC_DEFAULT] = RCS0,
2283 [I915_EXEC_RENDER] = RCS0,
  /src/sys/external/bsd/drm2/dist/drm/i915/gem/selftests/
i915_gem_context.c 1853 rq = igt_request_alloc(ctx, i915->engine[RCS0]);
1861 context_barrier_inject_fault = BIT(RCS0);
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
intel_overlay.c 1362 engine = dev_priv->engine[RCS0];

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