1 /* $NetBSD: intel_overlay.c,v 1.3 2021/12/19 11:48:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2009 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Daniel Vetter <daniel (at) ffwll.ch> 27 * 28 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: intel_overlay.c,v 1.3 2021/12/19 11:48:02 riastradh Exp $"); 33 34 #include <drm/drm_fourcc.h> 35 #include <drm/i915_drm.h> 36 37 #include "gem/i915_gem_pm.h" 38 #include "gt/intel_ring.h" 39 40 #include "i915_drv.h" 41 #include "i915_reg.h" 42 #include "intel_display_types.h" 43 #include "intel_frontbuffer.h" 44 #include "intel_overlay.h" 45 46 #include <linux/nbsd-namespace.h> 47 48 /* Limits for overlay size. According to intel doc, the real limits are: 49 * Y width: 4095, UV width (planar): 2047, Y height: 2047, 50 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use 51 * the mininum of both. */ 52 #define IMAGE_MAX_WIDTH 2048 53 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ 54 /* on 830 and 845 these large limits result in the card hanging */ 55 #define IMAGE_MAX_WIDTH_LEGACY 1024 56 #define IMAGE_MAX_HEIGHT_LEGACY 1088 57 58 /* overlay register definitions */ 59 /* OCMD register */ 60 #define OCMD_TILED_SURFACE (0x1<<19) 61 #define OCMD_MIRROR_MASK (0x3<<17) 62 #define OCMD_MIRROR_MODE (0x3<<17) 63 #define OCMD_MIRROR_HORIZONTAL (0x1<<17) 64 #define OCMD_MIRROR_VERTICAL (0x2<<17) 65 #define OCMD_MIRROR_BOTH (0x3<<17) 66 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ 67 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ 68 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ 69 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ 70 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) 71 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ 72 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ 73 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ 74 #define OCMD_YUV_422_PACKED (0x8<<10) 75 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ 76 #define OCMD_YUV_420_PLANAR (0xc<<10) 77 #define OCMD_YUV_422_PLANAR (0xd<<10) 78 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ 79 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) 80 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) 81 #define OCMD_BUF_TYPE_MASK (0x1<<5) 82 #define OCMD_BUF_TYPE_FRAME (0x0<<5) 83 #define OCMD_BUF_TYPE_FIELD (0x1<<5) 84 #define OCMD_TEST_MODE (0x1<<4) 85 #define OCMD_BUFFER_SELECT (0x3<<2) 86 #define OCMD_BUFFER0 (0x0<<2) 87 #define OCMD_BUFFER1 (0x1<<2) 88 #define OCMD_FIELD_SELECT (0x1<<2) 89 #define OCMD_FIELD0 (0x0<<1) 90 #define OCMD_FIELD1 (0x1<<1) 91 #define OCMD_ENABLE (0x1<<0) 92 93 /* OCONFIG register */ 94 #define OCONF_PIPE_MASK (0x1<<18) 95 #define OCONF_PIPE_A (0x0<<18) 96 #define OCONF_PIPE_B (0x1<<18) 97 #define OCONF_GAMMA2_ENABLE (0x1<<16) 98 #define OCONF_CSC_MODE_BT601 (0x0<<5) 99 #define OCONF_CSC_MODE_BT709 (0x1<<5) 100 #define OCONF_CSC_BYPASS (0x1<<4) 101 #define OCONF_CC_OUT_8BIT (0x1<<3) 102 #define OCONF_TEST_MODE (0x1<<2) 103 #define OCONF_THREE_LINE_BUFFER (0x1<<0) 104 #define OCONF_TWO_LINE_BUFFER (0x0<<0) 105 106 /* DCLRKM (dst-key) register */ 107 #define DST_KEY_ENABLE (0x1<<31) 108 #define CLK_RGB24_MASK 0x0 109 #define CLK_RGB16_MASK 0x070307 110 #define CLK_RGB15_MASK 0x070707 111 #define CLK_RGB8I_MASK 0xffffff 112 113 #define RGB16_TO_COLORKEY(c) \ 114 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) 115 #define RGB15_TO_COLORKEY(c) \ 116 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) 117 118 /* overlay flip addr flag */ 119 #define OFC_UPDATE 0x1 120 121 /* polyphase filter coefficients */ 122 #define N_HORIZ_Y_TAPS 5 123 #define N_VERT_Y_TAPS 3 124 #define N_HORIZ_UV_TAPS 3 125 #define N_VERT_UV_TAPS 3 126 #define N_PHASES 17 127 #define MAX_TAPS 5 128 129 /* memory bufferd overlay registers */ 130 struct overlay_registers { 131 u32 OBUF_0Y; 132 u32 OBUF_1Y; 133 u32 OBUF_0U; 134 u32 OBUF_0V; 135 u32 OBUF_1U; 136 u32 OBUF_1V; 137 u32 OSTRIDE; 138 u32 YRGB_VPH; 139 u32 UV_VPH; 140 u32 HORZ_PH; 141 u32 INIT_PHS; 142 u32 DWINPOS; 143 u32 DWINSZ; 144 u32 SWIDTH; 145 u32 SWIDTHSW; 146 u32 SHEIGHT; 147 u32 YRGBSCALE; 148 u32 UVSCALE; 149 u32 OCLRC0; 150 u32 OCLRC1; 151 u32 DCLRKV; 152 u32 DCLRKM; 153 u32 SCLRKVH; 154 u32 SCLRKVL; 155 u32 SCLRKEN; 156 u32 OCONFIG; 157 u32 OCMD; 158 u32 RESERVED1; /* 0x6C */ 159 u32 OSTART_0Y; 160 u32 OSTART_1Y; 161 u32 OSTART_0U; 162 u32 OSTART_0V; 163 u32 OSTART_1U; 164 u32 OSTART_1V; 165 u32 OTILEOFF_0Y; 166 u32 OTILEOFF_1Y; 167 u32 OTILEOFF_0U; 168 u32 OTILEOFF_0V; 169 u32 OTILEOFF_1U; 170 u32 OTILEOFF_1V; 171 u32 FASTHSCALE; /* 0xA0 */ 172 u32 UVSCALEV; /* 0xA4 */ 173 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ 174 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ 175 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; 176 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ 177 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; 178 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ 179 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; 180 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ 181 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; 182 }; 183 184 #ifdef __NetBSD__ /* XXX intel overlay iomem */ 185 # define __intel_overlay_iomem 186 # define __iomem __intel_overlay_iomem 187 188 static inline void 189 iowrite32(uint32_t value, uint32_t __intel_overlay_iomem *ptr) 190 { 191 192 __insn_barrier(); 193 *ptr = value; 194 } 195 #endif 196 197 struct intel_overlay { 198 struct drm_i915_private *i915; 199 struct intel_context *context; 200 struct intel_crtc *crtc; 201 struct i915_vma *vma; 202 struct i915_vma *old_vma; 203 bool active; 204 bool pfit_active; 205 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ 206 u32 color_key:24; 207 u32 color_key_enabled:1; 208 u32 brightness, contrast, saturation; 209 u32 old_xscale, old_yscale; 210 /* register access */ 211 struct drm_i915_gem_object *reg_bo; 212 struct overlay_registers __iomem *regs; 213 u32 flip_addr; 214 /* flip handling */ 215 struct i915_active last_flip; 216 void (*flip_complete)(struct intel_overlay *ovl); 217 }; 218 219 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv, 220 bool enable) 221 { 222 struct pci_dev *pdev = dev_priv->drm.pdev; 223 u8 val; 224 225 /* WA_OVERLAY_CLKGATE:alm */ 226 if (enable) 227 I915_WRITE(DSPCLK_GATE_D, 0); 228 else 229 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); 230 231 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */ 232 pci_bus_read_config_byte(pdev->bus, 233 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val); 234 if (enable) 235 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE; 236 else 237 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE; 238 pci_bus_write_config_byte(pdev->bus, 239 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val); 240 } 241 242 static struct i915_request * 243 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *)) 244 { 245 struct i915_request *rq; 246 int err; 247 248 overlay->flip_complete = fn; 249 250 rq = i915_request_create(overlay->context); 251 if (IS_ERR(rq)) 252 return rq; 253 254 err = i915_active_add_request(&overlay->last_flip, rq); 255 if (err) { 256 i915_request_add(rq); 257 return ERR_PTR(err); 258 } 259 260 return rq; 261 } 262 263 /* overlay needs to be disable in OCMD reg */ 264 static int intel_overlay_on(struct intel_overlay *overlay) 265 { 266 struct drm_i915_private *dev_priv = overlay->i915; 267 struct i915_request *rq; 268 u32 *cs; 269 270 WARN_ON(overlay->active); 271 272 rq = alloc_request(overlay, NULL); 273 if (IS_ERR(rq)) 274 return PTR_ERR(rq); 275 276 cs = intel_ring_begin(rq, 4); 277 if (IS_ERR(cs)) { 278 i915_request_add(rq); 279 return PTR_ERR(cs); 280 } 281 282 overlay->active = true; 283 284 if (IS_I830(dev_priv)) 285 i830_overlay_clock_gating(dev_priv, false); 286 287 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON; 288 *cs++ = overlay->flip_addr | OFC_UPDATE; 289 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 290 *cs++ = MI_NOOP; 291 intel_ring_advance(rq, cs); 292 293 i915_request_add(rq); 294 295 return i915_active_wait(&overlay->last_flip); 296 } 297 298 static void intel_overlay_flip_prepare(struct intel_overlay *overlay, 299 struct i915_vma *vma) 300 { 301 enum pipe pipe = overlay->crtc->pipe; 302 struct intel_frontbuffer *from = NULL, *to = NULL; 303 304 WARN_ON(overlay->old_vma); 305 306 if (overlay->vma) 307 from = intel_frontbuffer_get(overlay->vma->obj); 308 if (vma) 309 to = intel_frontbuffer_get(vma->obj); 310 311 intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe)); 312 313 if (to) 314 intel_frontbuffer_put(to); 315 if (from) 316 intel_frontbuffer_put(from); 317 318 intel_frontbuffer_flip_prepare(overlay->i915, 319 INTEL_FRONTBUFFER_OVERLAY(pipe)); 320 321 overlay->old_vma = overlay->vma; 322 if (vma) 323 overlay->vma = i915_vma_get(vma); 324 else 325 overlay->vma = NULL; 326 } 327 328 /* overlay needs to be enabled in OCMD reg */ 329 static int intel_overlay_continue(struct intel_overlay *overlay, 330 struct i915_vma *vma, 331 bool load_polyphase_filter) 332 { 333 struct drm_i915_private *dev_priv = overlay->i915; 334 struct i915_request *rq; 335 u32 flip_addr = overlay->flip_addr; 336 u32 tmp, *cs; 337 338 WARN_ON(!overlay->active); 339 340 if (load_polyphase_filter) 341 flip_addr |= OFC_UPDATE; 342 343 /* check for underruns */ 344 tmp = I915_READ(DOVSTA); 345 if (tmp & (1 << 17)) 346 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); 347 348 rq = alloc_request(overlay, NULL); 349 if (IS_ERR(rq)) 350 return PTR_ERR(rq); 351 352 cs = intel_ring_begin(rq, 2); 353 if (IS_ERR(cs)) { 354 i915_request_add(rq); 355 return PTR_ERR(cs); 356 } 357 358 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 359 *cs++ = flip_addr; 360 intel_ring_advance(rq, cs); 361 362 intel_overlay_flip_prepare(overlay, vma); 363 i915_request_add(rq); 364 365 return 0; 366 } 367 368 static void intel_overlay_release_old_vma(struct intel_overlay *overlay) 369 { 370 struct i915_vma *vma; 371 372 vma = fetch_and_zero(&overlay->old_vma); 373 if (WARN_ON(!vma)) 374 return; 375 376 intel_frontbuffer_flip_complete(overlay->i915, 377 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); 378 379 i915_gem_object_unpin_from_display_plane(vma); 380 i915_vma_put(vma); 381 } 382 383 static void 384 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) 385 { 386 intel_overlay_release_old_vma(overlay); 387 } 388 389 static void intel_overlay_off_tail(struct intel_overlay *overlay) 390 { 391 struct drm_i915_private *dev_priv = overlay->i915; 392 393 intel_overlay_release_old_vma(overlay); 394 395 overlay->crtc->overlay = NULL; 396 overlay->crtc = NULL; 397 overlay->active = false; 398 399 if (IS_I830(dev_priv)) 400 i830_overlay_clock_gating(dev_priv, true); 401 } 402 403 static void 404 intel_overlay_last_flip_retire(struct i915_active *active) 405 { 406 struct intel_overlay *overlay = 407 container_of(active, typeof(*overlay), last_flip); 408 409 if (overlay->flip_complete) 410 overlay->flip_complete(overlay); 411 } 412 413 /* overlay needs to be disabled in OCMD reg */ 414 static int intel_overlay_off(struct intel_overlay *overlay) 415 { 416 struct i915_request *rq; 417 u32 *cs, flip_addr = overlay->flip_addr; 418 419 WARN_ON(!overlay->active); 420 421 /* According to intel docs the overlay hw may hang (when switching 422 * off) without loading the filter coeffs. It is however unclear whether 423 * this applies to the disabling of the overlay or to the switching off 424 * of the hw. Do it in both cases */ 425 flip_addr |= OFC_UPDATE; 426 427 rq = alloc_request(overlay, intel_overlay_off_tail); 428 if (IS_ERR(rq)) 429 return PTR_ERR(rq); 430 431 cs = intel_ring_begin(rq, 6); 432 if (IS_ERR(cs)) { 433 i915_request_add(rq); 434 return PTR_ERR(cs); 435 } 436 437 /* wait for overlay to go idle */ 438 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE; 439 *cs++ = flip_addr; 440 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 441 442 /* turn overlay off */ 443 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF; 444 *cs++ = flip_addr; 445 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 446 447 intel_ring_advance(rq, cs); 448 449 intel_overlay_flip_prepare(overlay, NULL); 450 i915_request_add(rq); 451 452 return i915_active_wait(&overlay->last_flip); 453 } 454 455 /* recover from an interruption due to a signal 456 * We have to be careful not to repeat work forever an make forward progess. */ 457 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) 458 { 459 return i915_active_wait(&overlay->last_flip); 460 } 461 462 /* Wait for pending overlay flip and release old frame. 463 * Needs to be called before the overlay register are changed 464 * via intel_overlay_(un)map_regs 465 */ 466 static int intel_overlay_release_old_vid(struct intel_overlay *overlay) 467 { 468 struct drm_i915_private *dev_priv = overlay->i915; 469 struct i915_request *rq; 470 u32 *cs; 471 472 /* 473 * Only wait if there is actually an old frame to release to 474 * guarantee forward progress. 475 */ 476 if (!overlay->old_vma) 477 return 0; 478 479 if (!(I915_READ(GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { 480 intel_overlay_release_old_vid_tail(overlay); 481 return 0; 482 } 483 484 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail); 485 if (IS_ERR(rq)) 486 return PTR_ERR(rq); 487 488 cs = intel_ring_begin(rq, 2); 489 if (IS_ERR(cs)) { 490 i915_request_add(rq); 491 return PTR_ERR(cs); 492 } 493 494 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP; 495 *cs++ = MI_NOOP; 496 intel_ring_advance(rq, cs); 497 498 i915_request_add(rq); 499 500 return i915_active_wait(&overlay->last_flip); 501 } 502 503 void intel_overlay_reset(struct drm_i915_private *dev_priv) 504 { 505 struct intel_overlay *overlay = dev_priv->overlay; 506 507 if (!overlay) 508 return; 509 510 overlay->old_xscale = 0; 511 overlay->old_yscale = 0; 512 overlay->crtc = NULL; 513 overlay->active = false; 514 } 515 516 static int packed_depth_bytes(u32 format) 517 { 518 switch (format & I915_OVERLAY_DEPTH_MASK) { 519 case I915_OVERLAY_YUV422: 520 return 4; 521 case I915_OVERLAY_YUV411: 522 /* return 6; not implemented */ 523 default: 524 return -EINVAL; 525 } 526 } 527 528 static int packed_width_bytes(u32 format, short width) 529 { 530 switch (format & I915_OVERLAY_DEPTH_MASK) { 531 case I915_OVERLAY_YUV422: 532 return width << 1; 533 default: 534 return -EINVAL; 535 } 536 } 537 538 static int uv_hsubsampling(u32 format) 539 { 540 switch (format & I915_OVERLAY_DEPTH_MASK) { 541 case I915_OVERLAY_YUV422: 542 case I915_OVERLAY_YUV420: 543 return 2; 544 case I915_OVERLAY_YUV411: 545 case I915_OVERLAY_YUV410: 546 return 4; 547 default: 548 return -EINVAL; 549 } 550 } 551 552 static int uv_vsubsampling(u32 format) 553 { 554 switch (format & I915_OVERLAY_DEPTH_MASK) { 555 case I915_OVERLAY_YUV420: 556 case I915_OVERLAY_YUV410: 557 return 2; 558 case I915_OVERLAY_YUV422: 559 case I915_OVERLAY_YUV411: 560 return 1; 561 default: 562 return -EINVAL; 563 } 564 } 565 566 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width) 567 { 568 u32 sw; 569 570 if (IS_GEN(dev_priv, 2)) 571 sw = ALIGN((offset & 31) + width, 32); 572 else 573 sw = ALIGN((offset & 63) + width, 64); 574 575 if (sw == 0) 576 return 0; 577 578 return (sw - 32) >> 3; 579 } 580 581 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = { 582 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, }, 583 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, }, 584 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, }, 585 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, }, 586 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, }, 587 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, }, 588 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, }, 589 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, }, 590 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, }, 591 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, }, 592 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, }, 593 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, }, 594 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, }, 595 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, }, 596 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, }, 597 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, }, 598 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, }, 599 }; 600 601 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = { 602 [ 0] = { 0x3000, 0x1800, 0x1800, }, 603 [ 1] = { 0xb000, 0x18d0, 0x2e60, }, 604 [ 2] = { 0xb000, 0x1990, 0x2ce0, }, 605 [ 3] = { 0xb020, 0x1a68, 0x2b40, }, 606 [ 4] = { 0xb040, 0x1b20, 0x29e0, }, 607 [ 5] = { 0xb060, 0x1bd8, 0x2880, }, 608 [ 6] = { 0xb080, 0x1c88, 0x3e60, }, 609 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, }, 610 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, }, 611 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, }, 612 [10] = { 0xb100, 0x1eb8, 0x3620, }, 613 [11] = { 0xb100, 0x1f18, 0x34a0, }, 614 [12] = { 0xb100, 0x1f68, 0x3360, }, 615 [13] = { 0xb0e0, 0x1fa8, 0x3240, }, 616 [14] = { 0xb0c0, 0x1fe0, 0x3140, }, 617 [15] = { 0xb060, 0x1ff0, 0x30a0, }, 618 [16] = { 0x3000, 0x0800, 0x3000, }, 619 }; 620 621 static void update_polyphase_filter(struct overlay_registers __iomem *regs) 622 { 623 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); 624 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, 625 sizeof(uv_static_hcoeffs)); 626 } 627 628 static bool update_scaling_factors(struct intel_overlay *overlay, 629 struct overlay_registers __iomem *regs, 630 struct drm_intel_overlay_put_image *params) 631 { 632 /* fixed point with a 12 bit shift */ 633 u32 xscale, yscale, xscale_UV, yscale_UV; 634 #define FP_SHIFT 12 635 #define FRACT_MASK 0xfff 636 bool scale_changed = false; 637 int uv_hscale = uv_hsubsampling(params->flags); 638 int uv_vscale = uv_vsubsampling(params->flags); 639 640 if (params->dst_width > 1) 641 xscale = ((params->src_scan_width - 1) << FP_SHIFT) / 642 params->dst_width; 643 else 644 xscale = 1 << FP_SHIFT; 645 646 if (params->dst_height > 1) 647 yscale = ((params->src_scan_height - 1) << FP_SHIFT) / 648 params->dst_height; 649 else 650 yscale = 1 << FP_SHIFT; 651 652 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ 653 xscale_UV = xscale/uv_hscale; 654 yscale_UV = yscale/uv_vscale; 655 /* make the Y scale to UV scale ratio an exact multiply */ 656 xscale = xscale_UV * uv_hscale; 657 yscale = yscale_UV * uv_vscale; 658 /*} else { 659 xscale_UV = 0; 660 yscale_UV = 0; 661 }*/ 662 663 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) 664 scale_changed = true; 665 overlay->old_xscale = xscale; 666 overlay->old_yscale = yscale; 667 668 iowrite32(((yscale & FRACT_MASK) << 20) | 669 ((xscale >> FP_SHIFT) << 16) | 670 ((xscale & FRACT_MASK) << 3), 671 ®s->YRGBSCALE); 672 673 iowrite32(((yscale_UV & FRACT_MASK) << 20) | 674 ((xscale_UV >> FP_SHIFT) << 16) | 675 ((xscale_UV & FRACT_MASK) << 3), 676 ®s->UVSCALE); 677 678 iowrite32((((yscale >> FP_SHIFT) << 16) | 679 ((yscale_UV >> FP_SHIFT) << 0)), 680 ®s->UVSCALEV); 681 682 if (scale_changed) 683 update_polyphase_filter(regs); 684 685 return scale_changed; 686 } 687 688 static void update_colorkey(struct intel_overlay *overlay, 689 struct overlay_registers __iomem *regs) 690 { 691 const struct intel_plane_state *state = 692 to_intel_plane_state(overlay->crtc->base.primary->state); 693 u32 key = overlay->color_key; 694 u32 format = 0; 695 u32 flags = 0; 696 697 if (overlay->color_key_enabled) 698 flags |= DST_KEY_ENABLE; 699 700 if (state->uapi.visible) 701 format = state->hw.fb->format->format; 702 703 switch (format) { 704 case DRM_FORMAT_C8: 705 key = 0; 706 flags |= CLK_RGB8I_MASK; 707 break; 708 case DRM_FORMAT_XRGB1555: 709 key = RGB15_TO_COLORKEY(key); 710 flags |= CLK_RGB15_MASK; 711 break; 712 case DRM_FORMAT_RGB565: 713 key = RGB16_TO_COLORKEY(key); 714 flags |= CLK_RGB16_MASK; 715 break; 716 default: 717 flags |= CLK_RGB24_MASK; 718 break; 719 } 720 721 iowrite32(key, ®s->DCLRKV); 722 iowrite32(flags, ®s->DCLRKM); 723 } 724 725 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params) 726 { 727 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; 728 729 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 730 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 731 case I915_OVERLAY_YUV422: 732 cmd |= OCMD_YUV_422_PLANAR; 733 break; 734 case I915_OVERLAY_YUV420: 735 cmd |= OCMD_YUV_420_PLANAR; 736 break; 737 case I915_OVERLAY_YUV411: 738 case I915_OVERLAY_YUV410: 739 cmd |= OCMD_YUV_410_PLANAR; 740 break; 741 } 742 } else { /* YUV packed */ 743 switch (params->flags & I915_OVERLAY_DEPTH_MASK) { 744 case I915_OVERLAY_YUV422: 745 cmd |= OCMD_YUV_422_PACKED; 746 break; 747 case I915_OVERLAY_YUV411: 748 cmd |= OCMD_YUV_411_PACKED; 749 break; 750 } 751 752 switch (params->flags & I915_OVERLAY_SWAP_MASK) { 753 case I915_OVERLAY_NO_SWAP: 754 break; 755 case I915_OVERLAY_UV_SWAP: 756 cmd |= OCMD_UV_SWAP; 757 break; 758 case I915_OVERLAY_Y_SWAP: 759 cmd |= OCMD_Y_SWAP; 760 break; 761 case I915_OVERLAY_Y_AND_UV_SWAP: 762 cmd |= OCMD_Y_AND_UV_SWAP; 763 break; 764 } 765 } 766 767 return cmd; 768 } 769 770 static int intel_overlay_do_put_image(struct intel_overlay *overlay, 771 struct drm_i915_gem_object *new_bo, 772 struct drm_intel_overlay_put_image *params) 773 { 774 struct overlay_registers __iomem *regs = overlay->regs; 775 struct drm_i915_private *dev_priv = overlay->i915; 776 u32 swidth, swidthsw, sheight, ostride; 777 enum pipe pipe = overlay->crtc->pipe; 778 bool scale_changed = false; 779 struct i915_vma *vma; 780 int ret, tmp_width; 781 782 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 783 784 ret = intel_overlay_release_old_vid(overlay); 785 if (ret != 0) 786 return ret; 787 788 atomic_inc(&dev_priv->gpu_error.pending_fb_pin); 789 790 vma = i915_gem_object_pin_to_display_plane(new_bo, 791 0, NULL, PIN_MAPPABLE); 792 if (IS_ERR(vma)) { 793 ret = PTR_ERR(vma); 794 goto out_pin_section; 795 } 796 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB); 797 798 if (!overlay->active) { 799 u32 oconfig; 800 801 oconfig = OCONF_CC_OUT_8BIT; 802 if (IS_GEN(dev_priv, 4)) 803 oconfig |= OCONF_CSC_MODE_BT709; 804 oconfig |= pipe == 0 ? 805 OCONF_PIPE_A : OCONF_PIPE_B; 806 iowrite32(oconfig, ®s->OCONFIG); 807 808 ret = intel_overlay_on(overlay); 809 if (ret != 0) 810 goto out_unpin; 811 } 812 813 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS); 814 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ); 815 816 if (params->flags & I915_OVERLAY_YUV_PACKED) 817 tmp_width = packed_width_bytes(params->flags, 818 params->src_width); 819 else 820 tmp_width = params->src_width; 821 822 swidth = params->src_width; 823 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width); 824 sheight = params->src_height; 825 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y); 826 ostride = params->stride_Y; 827 828 if (params->flags & I915_OVERLAY_YUV_PLANAR) { 829 int uv_hscale = uv_hsubsampling(params->flags); 830 int uv_vscale = uv_vsubsampling(params->flags); 831 u32 tmp_U, tmp_V; 832 833 swidth |= (params->src_width / uv_hscale) << 16; 834 sheight |= (params->src_height / uv_vscale) << 16; 835 836 tmp_U = calc_swidthsw(dev_priv, params->offset_U, 837 params->src_width / uv_hscale); 838 tmp_V = calc_swidthsw(dev_priv, params->offset_V, 839 params->src_width / uv_hscale); 840 swidthsw |= max(tmp_U, tmp_V) << 16; 841 842 iowrite32(i915_ggtt_offset(vma) + params->offset_U, 843 ®s->OBUF_0U); 844 iowrite32(i915_ggtt_offset(vma) + params->offset_V, 845 ®s->OBUF_0V); 846 847 ostride |= params->stride_UV << 16; 848 } 849 850 iowrite32(swidth, ®s->SWIDTH); 851 iowrite32(swidthsw, ®s->SWIDTHSW); 852 iowrite32(sheight, ®s->SHEIGHT); 853 iowrite32(ostride, ®s->OSTRIDE); 854 855 scale_changed = update_scaling_factors(overlay, regs, params); 856 857 update_colorkey(overlay, regs); 858 859 iowrite32(overlay_cmd_reg(params), ®s->OCMD); 860 861 ret = intel_overlay_continue(overlay, vma, scale_changed); 862 if (ret) 863 goto out_unpin; 864 865 return 0; 866 867 out_unpin: 868 i915_gem_object_unpin_from_display_plane(vma); 869 out_pin_section: 870 atomic_dec(&dev_priv->gpu_error.pending_fb_pin); 871 872 return ret; 873 } 874 875 int intel_overlay_switch_off(struct intel_overlay *overlay) 876 { 877 struct drm_i915_private *dev_priv = overlay->i915; 878 int ret; 879 880 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 881 882 ret = intel_overlay_recover_from_interrupt(overlay); 883 if (ret != 0) 884 return ret; 885 886 if (!overlay->active) 887 return 0; 888 889 ret = intel_overlay_release_old_vid(overlay); 890 if (ret != 0) 891 return ret; 892 893 iowrite32(0, &overlay->regs->OCMD); 894 895 return intel_overlay_off(overlay); 896 } 897 898 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, 899 struct intel_crtc *crtc) 900 { 901 if (!crtc->active) 902 return -EINVAL; 903 904 /* can't use the overlay with double wide pipe */ 905 if (crtc->config->double_wide) 906 return -EINVAL; 907 908 return 0; 909 } 910 911 static void update_pfit_vscale_ratio(struct intel_overlay *overlay) 912 { 913 struct drm_i915_private *dev_priv = overlay->i915; 914 u32 pfit_control = I915_READ(PFIT_CONTROL); 915 u32 ratio; 916 917 /* XXX: This is not the same logic as in the xorg driver, but more in 918 * line with the intel documentation for the i965 919 */ 920 if (INTEL_GEN(dev_priv) >= 4) { 921 /* on i965 use the PGM reg to read out the autoscaler values */ 922 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; 923 } else { 924 if (pfit_control & VERT_AUTO_SCALE) 925 ratio = I915_READ(PFIT_AUTO_RATIOS); 926 else 927 ratio = I915_READ(PFIT_PGM_RATIOS); 928 ratio >>= PFIT_VERT_SCALE_SHIFT; 929 } 930 931 overlay->pfit_vscale_ratio = ratio; 932 } 933 934 static int check_overlay_dst(struct intel_overlay *overlay, 935 struct drm_intel_overlay_put_image *rec) 936 { 937 const struct intel_crtc_state *pipe_config = 938 overlay->crtc->config; 939 940 if (rec->dst_x < pipe_config->pipe_src_w && 941 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w && 942 rec->dst_y < pipe_config->pipe_src_h && 943 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h) 944 return 0; 945 else 946 return -EINVAL; 947 } 948 949 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec) 950 { 951 u32 tmp; 952 953 /* downscaling limit is 8.0 */ 954 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16; 955 if (tmp > 7) 956 return -EINVAL; 957 958 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16; 959 if (tmp > 7) 960 return -EINVAL; 961 962 return 0; 963 } 964 965 static int check_overlay_src(struct drm_i915_private *dev_priv, 966 struct drm_intel_overlay_put_image *rec, 967 struct drm_i915_gem_object *new_bo) 968 { 969 int uv_hscale = uv_hsubsampling(rec->flags); 970 int uv_vscale = uv_vsubsampling(rec->flags); 971 u32 stride_mask; 972 int depth; 973 u32 tmp; 974 975 /* check src dimensions */ 976 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) { 977 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || 978 rec->src_width > IMAGE_MAX_WIDTH_LEGACY) 979 return -EINVAL; 980 } else { 981 if (rec->src_height > IMAGE_MAX_HEIGHT || 982 rec->src_width > IMAGE_MAX_WIDTH) 983 return -EINVAL; 984 } 985 986 /* better safe than sorry, use 4 as the maximal subsampling ratio */ 987 if (rec->src_height < N_VERT_Y_TAPS*4 || 988 rec->src_width < N_HORIZ_Y_TAPS*4) 989 return -EINVAL; 990 991 /* check alignment constraints */ 992 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 993 case I915_OVERLAY_RGB: 994 /* not implemented */ 995 return -EINVAL; 996 997 case I915_OVERLAY_YUV_PACKED: 998 if (uv_vscale != 1) 999 return -EINVAL; 1000 1001 depth = packed_depth_bytes(rec->flags); 1002 if (depth < 0) 1003 return depth; 1004 1005 /* ignore UV planes */ 1006 rec->stride_UV = 0; 1007 rec->offset_U = 0; 1008 rec->offset_V = 0; 1009 /* check pixel alignment */ 1010 if (rec->offset_Y % depth) 1011 return -EINVAL; 1012 break; 1013 1014 case I915_OVERLAY_YUV_PLANAR: 1015 if (uv_vscale < 0 || uv_hscale < 0) 1016 return -EINVAL; 1017 /* no offset restrictions for planar formats */ 1018 break; 1019 1020 default: 1021 return -EINVAL; 1022 } 1023 1024 if (rec->src_width % uv_hscale) 1025 return -EINVAL; 1026 1027 /* stride checking */ 1028 if (IS_I830(dev_priv) || IS_I845G(dev_priv)) 1029 stride_mask = 255; 1030 else 1031 stride_mask = 63; 1032 1033 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) 1034 return -EINVAL; 1035 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512) 1036 return -EINVAL; 1037 1038 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? 1039 4096 : 8192; 1040 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) 1041 return -EINVAL; 1042 1043 /* check buffer dimensions */ 1044 switch (rec->flags & I915_OVERLAY_TYPE_MASK) { 1045 case I915_OVERLAY_RGB: 1046 case I915_OVERLAY_YUV_PACKED: 1047 /* always 4 Y values per depth pixels */ 1048 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) 1049 return -EINVAL; 1050 1051 tmp = rec->stride_Y*rec->src_height; 1052 if (rec->offset_Y + tmp > new_bo->base.size) 1053 return -EINVAL; 1054 break; 1055 1056 case I915_OVERLAY_YUV_PLANAR: 1057 if (rec->src_width > rec->stride_Y) 1058 return -EINVAL; 1059 if (rec->src_width/uv_hscale > rec->stride_UV) 1060 return -EINVAL; 1061 1062 tmp = rec->stride_Y * rec->src_height; 1063 if (rec->offset_Y + tmp > new_bo->base.size) 1064 return -EINVAL; 1065 1066 tmp = rec->stride_UV * (rec->src_height / uv_vscale); 1067 if (rec->offset_U + tmp > new_bo->base.size || 1068 rec->offset_V + tmp > new_bo->base.size) 1069 return -EINVAL; 1070 break; 1071 } 1072 1073 return 0; 1074 } 1075 1076 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data, 1077 struct drm_file *file_priv) 1078 { 1079 struct drm_intel_overlay_put_image *params = data; 1080 struct drm_i915_private *dev_priv = to_i915(dev); 1081 struct intel_overlay *overlay; 1082 struct drm_crtc *drmmode_crtc; 1083 struct intel_crtc *crtc; 1084 struct drm_i915_gem_object *new_bo; 1085 int ret; 1086 1087 overlay = dev_priv->overlay; 1088 if (!overlay) { 1089 DRM_DEBUG("userspace bug: no overlay\n"); 1090 return -ENODEV; 1091 } 1092 1093 if (!(params->flags & I915_OVERLAY_ENABLE)) { 1094 drm_modeset_lock_all(dev); 1095 ret = intel_overlay_switch_off(overlay); 1096 drm_modeset_unlock_all(dev); 1097 1098 return ret; 1099 } 1100 1101 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id); 1102 if (!drmmode_crtc) 1103 return -ENOENT; 1104 crtc = to_intel_crtc(drmmode_crtc); 1105 1106 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle); 1107 if (!new_bo) 1108 return -ENOENT; 1109 1110 drm_modeset_lock_all(dev); 1111 1112 if (i915_gem_object_is_tiled(new_bo)) { 1113 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); 1114 ret = -EINVAL; 1115 goto out_unlock; 1116 } 1117 1118 ret = intel_overlay_recover_from_interrupt(overlay); 1119 if (ret != 0) 1120 goto out_unlock; 1121 1122 if (overlay->crtc != crtc) { 1123 ret = intel_overlay_switch_off(overlay); 1124 if (ret != 0) 1125 goto out_unlock; 1126 1127 ret = check_overlay_possible_on_crtc(overlay, crtc); 1128 if (ret != 0) 1129 goto out_unlock; 1130 1131 overlay->crtc = crtc; 1132 crtc->overlay = overlay; 1133 1134 /* line too wide, i.e. one-line-mode */ 1135 if (crtc->config->pipe_src_w > 1024 && 1136 crtc->config->gmch_pfit.control & PFIT_ENABLE) { 1137 overlay->pfit_active = true; 1138 update_pfit_vscale_ratio(overlay); 1139 } else 1140 overlay->pfit_active = false; 1141 } 1142 1143 ret = check_overlay_dst(overlay, params); 1144 if (ret != 0) 1145 goto out_unlock; 1146 1147 if (overlay->pfit_active) { 1148 params->dst_y = (((u32)params->dst_y << 12) / 1149 overlay->pfit_vscale_ratio); 1150 /* shifting right rounds downwards, so add 1 */ 1151 params->dst_height = (((u32)params->dst_height << 12) / 1152 overlay->pfit_vscale_ratio) + 1; 1153 } 1154 1155 if (params->src_scan_height > params->src_height || 1156 params->src_scan_width > params->src_width) { 1157 ret = -EINVAL; 1158 goto out_unlock; 1159 } 1160 1161 ret = check_overlay_src(dev_priv, params, new_bo); 1162 if (ret != 0) 1163 goto out_unlock; 1164 1165 /* Check scaling after src size to prevent a divide-by-zero. */ 1166 ret = check_overlay_scaling(params); 1167 if (ret != 0) 1168 goto out_unlock; 1169 1170 ret = intel_overlay_do_put_image(overlay, new_bo, params); 1171 if (ret != 0) 1172 goto out_unlock; 1173 1174 drm_modeset_unlock_all(dev); 1175 i915_gem_object_put(new_bo); 1176 1177 return 0; 1178 1179 out_unlock: 1180 drm_modeset_unlock_all(dev); 1181 i915_gem_object_put(new_bo); 1182 1183 return ret; 1184 } 1185 1186 static void update_reg_attrs(struct intel_overlay *overlay, 1187 struct overlay_registers __iomem *regs) 1188 { 1189 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), 1190 ®s->OCLRC0); 1191 iowrite32(overlay->saturation, ®s->OCLRC1); 1192 } 1193 1194 static bool check_gamma_bounds(u32 gamma1, u32 gamma2) 1195 { 1196 int i; 1197 1198 if (gamma1 & 0xff000000 || gamma2 & 0xff000000) 1199 return false; 1200 1201 for (i = 0; i < 3; i++) { 1202 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) 1203 return false; 1204 } 1205 1206 return true; 1207 } 1208 1209 static bool check_gamma5_errata(u32 gamma5) 1210 { 1211 int i; 1212 1213 for (i = 0; i < 3; i++) { 1214 if (((gamma5 >> i*8) & 0xff) == 0x80) 1215 return false; 1216 } 1217 1218 return true; 1219 } 1220 1221 static int check_gamma(struct drm_intel_overlay_attrs *attrs) 1222 { 1223 if (!check_gamma_bounds(0, attrs->gamma0) || 1224 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || 1225 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || 1226 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || 1227 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || 1228 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || 1229 !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) 1230 return -EINVAL; 1231 1232 if (!check_gamma5_errata(attrs->gamma5)) 1233 return -EINVAL; 1234 1235 return 0; 1236 } 1237 1238 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, 1239 struct drm_file *file_priv) 1240 { 1241 struct drm_intel_overlay_attrs *attrs = data; 1242 struct drm_i915_private *dev_priv = to_i915(dev); 1243 struct intel_overlay *overlay; 1244 int ret; 1245 1246 overlay = dev_priv->overlay; 1247 if (!overlay) { 1248 DRM_DEBUG("userspace bug: no overlay\n"); 1249 return -ENODEV; 1250 } 1251 1252 drm_modeset_lock_all(dev); 1253 1254 ret = -EINVAL; 1255 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { 1256 attrs->color_key = overlay->color_key; 1257 attrs->brightness = overlay->brightness; 1258 attrs->contrast = overlay->contrast; 1259 attrs->saturation = overlay->saturation; 1260 1261 if (!IS_GEN(dev_priv, 2)) { 1262 attrs->gamma0 = I915_READ(OGAMC0); 1263 attrs->gamma1 = I915_READ(OGAMC1); 1264 attrs->gamma2 = I915_READ(OGAMC2); 1265 attrs->gamma3 = I915_READ(OGAMC3); 1266 attrs->gamma4 = I915_READ(OGAMC4); 1267 attrs->gamma5 = I915_READ(OGAMC5); 1268 } 1269 } else { 1270 if (attrs->brightness < -128 || attrs->brightness > 127) 1271 goto out_unlock; 1272 if (attrs->contrast > 255) 1273 goto out_unlock; 1274 if (attrs->saturation > 1023) 1275 goto out_unlock; 1276 1277 overlay->color_key = attrs->color_key; 1278 overlay->brightness = attrs->brightness; 1279 overlay->contrast = attrs->contrast; 1280 overlay->saturation = attrs->saturation; 1281 1282 update_reg_attrs(overlay, overlay->regs); 1283 1284 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { 1285 if (IS_GEN(dev_priv, 2)) 1286 goto out_unlock; 1287 1288 if (overlay->active) { 1289 ret = -EBUSY; 1290 goto out_unlock; 1291 } 1292 1293 ret = check_gamma(attrs); 1294 if (ret) 1295 goto out_unlock; 1296 1297 I915_WRITE(OGAMC0, attrs->gamma0); 1298 I915_WRITE(OGAMC1, attrs->gamma1); 1299 I915_WRITE(OGAMC2, attrs->gamma2); 1300 I915_WRITE(OGAMC3, attrs->gamma3); 1301 I915_WRITE(OGAMC4, attrs->gamma4); 1302 I915_WRITE(OGAMC5, attrs->gamma5); 1303 } 1304 } 1305 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0; 1306 1307 ret = 0; 1308 out_unlock: 1309 drm_modeset_unlock_all(dev); 1310 1311 return ret; 1312 } 1313 1314 static int get_registers(struct intel_overlay *overlay, bool use_phys) 1315 { 1316 struct drm_i915_private *i915 = overlay->i915; 1317 struct drm_i915_gem_object *obj; 1318 struct i915_vma *vma; 1319 int err; 1320 1321 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE); 1322 if (IS_ERR(obj)) 1323 obj = i915_gem_object_create_internal(i915, PAGE_SIZE); 1324 if (IS_ERR(obj)) 1325 return PTR_ERR(obj); 1326 1327 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); 1328 if (IS_ERR(vma)) { 1329 err = PTR_ERR(vma); 1330 goto err_put_bo; 1331 } 1332 1333 if (use_phys) 1334 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl); 1335 else 1336 overlay->flip_addr = i915_ggtt_offset(vma); 1337 overlay->regs = i915_vma_pin_iomap(vma); 1338 i915_vma_unpin(vma); 1339 1340 if (IS_ERR(overlay->regs)) { 1341 err = PTR_ERR(overlay->regs); 1342 goto err_put_bo; 1343 } 1344 1345 overlay->reg_bo = obj; 1346 return 0; 1347 1348 err_put_bo: 1349 i915_gem_object_put(obj); 1350 return err; 1351 } 1352 1353 void intel_overlay_setup(struct drm_i915_private *dev_priv) 1354 { 1355 struct intel_overlay *overlay; 1356 struct intel_engine_cs *engine; 1357 int ret; 1358 1359 if (!HAS_OVERLAY(dev_priv)) 1360 return; 1361 1362 engine = dev_priv->engine[RCS0]; 1363 if (!engine || !engine->kernel_context) 1364 return; 1365 1366 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); 1367 if (!overlay) 1368 return; 1369 1370 overlay->i915 = dev_priv; 1371 overlay->context = engine->kernel_context; 1372 GEM_BUG_ON(!overlay->context); 1373 1374 overlay->color_key = 0x0101fe; 1375 overlay->color_key_enabled = true; 1376 overlay->brightness = -19; 1377 overlay->contrast = 75; 1378 overlay->saturation = 146; 1379 1380 i915_active_init(&overlay->last_flip, 1381 NULL, intel_overlay_last_flip_retire); 1382 1383 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv)); 1384 if (ret) 1385 goto out_free; 1386 1387 memset_io(overlay->regs, 0, sizeof(struct overlay_registers)); 1388 update_polyphase_filter(overlay->regs); 1389 update_reg_attrs(overlay, overlay->regs); 1390 1391 dev_priv->overlay = overlay; 1392 DRM_INFO("Initialized overlay support.\n"); 1393 return; 1394 1395 out_free: 1396 kfree(overlay); 1397 } 1398 1399 void intel_overlay_cleanup(struct drm_i915_private *dev_priv) 1400 { 1401 struct intel_overlay *overlay; 1402 1403 overlay = fetch_and_zero(&dev_priv->overlay); 1404 if (!overlay) 1405 return; 1406 1407 /* 1408 * The bo's should be free'd by the generic code already. 1409 * Furthermore modesetting teardown happens beforehand so the 1410 * hardware should be off already. 1411 */ 1412 WARN_ON(overlay->active); 1413 1414 i915_gem_object_put(overlay->reg_bo); 1415 i915_active_fini(&overlay->last_flip); 1416 1417 kfree(overlay); 1418 } 1419 1420 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) 1421 1422 struct intel_overlay_error_state { 1423 struct overlay_registers regs; 1424 unsigned long base; 1425 u32 dovsta; 1426 u32 isr; 1427 }; 1428 1429 struct intel_overlay_error_state * 1430 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) 1431 { 1432 struct intel_overlay *overlay = dev_priv->overlay; 1433 struct intel_overlay_error_state *error; 1434 1435 if (!overlay || !overlay->active) 1436 return NULL; 1437 1438 error = kmalloc(sizeof(*error), GFP_ATOMIC); 1439 if (error == NULL) 1440 return NULL; 1441 1442 error->dovsta = I915_READ(DOVSTA); 1443 error->isr = I915_READ(GEN2_ISR); 1444 error->base = overlay->flip_addr; 1445 1446 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs)); 1447 1448 return error; 1449 } 1450 1451 void 1452 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, 1453 struct intel_overlay_error_state *error) 1454 { 1455 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", 1456 error->dovsta, error->isr); 1457 i915_error_printf(m, " Register file at 0x%08lx:\n", 1458 error->base); 1459 1460 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) 1461 P(OBUF_0Y); 1462 P(OBUF_1Y); 1463 P(OBUF_0U); 1464 P(OBUF_0V); 1465 P(OBUF_1U); 1466 P(OBUF_1V); 1467 P(OSTRIDE); 1468 P(YRGB_VPH); 1469 P(UV_VPH); 1470 P(HORZ_PH); 1471 P(INIT_PHS); 1472 P(DWINPOS); 1473 P(DWINSZ); 1474 P(SWIDTH); 1475 P(SWIDTHSW); 1476 P(SHEIGHT); 1477 P(YRGBSCALE); 1478 P(UVSCALE); 1479 P(OCLRC0); 1480 P(OCLRC1); 1481 P(DCLRKV); 1482 P(DCLRKM); 1483 P(SCLRKVH); 1484 P(SCLRKVL); 1485 P(SCLRKEN); 1486 P(OCONFIG); 1487 P(OCMD); 1488 P(OSTART_0Y); 1489 P(OSTART_1Y); 1490 P(OSTART_0U); 1491 P(OSTART_0V); 1492 P(OSTART_1U); 1493 P(OSTART_1V); 1494 P(OTILEOFF_0Y); 1495 P(OTILEOFF_1Y); 1496 P(OTILEOFF_0U); 1497 P(OTILEOFF_0V); 1498 P(OTILEOFF_1U); 1499 P(OTILEOFF_1V); 1500 P(FASTHSCALE); 1501 P(UVSCALEV); 1502 #undef P 1503 } 1504 1505 #endif 1506
Indexes created Sat Sep 20 22:09:52 GMT 2025