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    Searched refs:REG_RD (Results 1 - 9 of 9) sorted by relevancy

  /src/sys/arch/evbarm/stand/bootimx23/
power_prep.c 96 tmp_r = REG_RD(PWR_5VCTRL);
114 if (REG_RD(PWR_STATUS) & HW_POWER_STS_VBUSVALID)
137 tmp_r = REG_RD(PWR_DCLIMITS);
154 tmp_r = REG_RD(PWR_DCDC4P2);
168 tmp_r = REG_RD(PWR_DCDC4P2);
175 tmp_r = REG_RD(PWR_5VCTRL);
193 tmp_r = REG_RD(PWR_DCDC4P2);
233 tmp_r = REG_RD(PWR_VDDDCTRL);
240 tmp_r = REG_RD(PWR_VDDDCTRL);
246 tmp_r = REG_RD(PWR_VDDDCTRL)
    [all...]
clock_prep.c 72 while(!(REG_RD(CLKCTRL_PLL1) & HW_CLKCTRL_PLLCTRL1))
114 while (REG_RD(CLKCTRL_HBUS) & HW_CLKCTRL_HBUS_BUSY)
117 tmp_r = REG_RD(CLKCTRL_HBUS);
122 while (REG_RD(CLKCTRL_HBUS) & HW_CLKCTRL_HBUS_BUSY)
170 while (REG_RD(CLKCTRL_EMI) &
174 tmp_r = REG_RD(CLKCTRL_EMI);
189 tmp_r = REG_RD(CLKCTRL_SSP);
193 while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY)
196 tmp_r = REG_RD(CLKCTRL_SSP);
201 while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY
    [all...]
emi_prep.c 69 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL08);
76 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL08);
86 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL16);
90 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL16);
133 reg = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL18);
common.h 35 #define REG_RD(reg) *(volatile uint32_t *)(reg)
args_prep.c 115 while (REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS) < PROMPT_DELAY) {
119 REG_RD(HW_UARTDBG_BASE + HW_UARTDBGDR); /* Flush. */
  /src/sys/arch/evbarm/imx23_olinuxino/
imx23_olinuxino_machdep.c 82 #define REG_RD(reg) *(volatile uint32_t *)(reg)
247 (REG_RD(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU) |
288 start = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS);
291 now = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS);
324 tmp_r = REG_RD(PWR_VDDIOCTRL);
331 tmp_r = REG_RD(PWR_VDDIOCTRL);
337 tmp_r = REG_RD(PWR_VDDIOCTRL);
348 tmp_r = REG_RD(PWR_VDDIOCTRL);
364 tmp_r = REG_RD(CLKCTRL_SSP);
368 while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY
    [all...]
  /src/sys/arch/arm/imx/
imx23_platform.c 55 #define REG_RD(reg) *(volatile uint32_t *)(reg)
132 start = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS);
135 now = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS);
  /src/sys/dev/pci/
if_bnx.c 651 sc->bnx_chipid = REG_RD(sc, BNX_MISC_ID);
732 val = REG_RD(sc, BNX_PCICFG_MISC_STATUS);
738 clkreg = REG_RD(sc, BNX_PCICFG_PCI_CLOCK_CONTROL_BITS);
1072 val = REG_RD(sc, BNX_CTX_CTX_CTRL);
1117 data = REG_RD(sc, BNX_EMAC_MDIO_MODE);
1121 REG_RD(sc, BNX_EMAC_MDIO_MODE);
1134 data = REG_RD(sc, BNX_EMAC_MDIO_COMM);
1138 data = REG_RD(sc, BNX_EMAC_MDIO_COMM);
1150 data = REG_RD(sc, BNX_EMAC_MDIO_COMM);
1159 data = REG_RD(sc, BNX_EMAC_MDIO_MODE)
    [all...]
if_bnxvar.h 87 #define REG_RD(sc, reg) bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg)
91 #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
92 #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))

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