| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_vmid.c | 80 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0,
82 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0,
85 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0,
87 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0,
94 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0,
97 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0,
|
| amdgpu_dcn20_mpc.c | 71 REG_SET(MPCC_TOP_GAIN[mpcc_id], 0, MPCC_TOP_GAIN, blnd_cfg->top_gain);
72 REG_SET(MPCC_BOT_GAIN_INSIDE[mpcc_id], 0, MPCC_BOT_GAIN_INSIDE, blnd_cfg->bottom_inside_gain);
73 REG_SET(MPCC_BOT_GAIN_OUTSIDE[mpcc_id], 0, MPCC_BOT_GAIN_OUTSIDE, blnd_cfg->bottom_outside_gain);
148 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
188 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
204 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
247 REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
284 REG_SET(MPCC_MEM_PWR_CTRL[mpcc_id], 0,
299 REG_SET(MPCC_OGAM_LUT_INDEX[mpcc_id], 0, MPCC_OGAM_LUT_INDEX, 0);
394 REG_SET(MPCC_OGAM_LUT_DATA[mpcc_id], 0, MPCC_OGAM_LUT_DATA, rgb[i].red_reg)
[all...] |
| amdgpu_dcn20_optc.c | 207 REG_SET(OPTC_BYTES_PER_PIXEL, 0,
235 REG_SET(OPTC_MEMORY_CONFIG, 0,
252 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
267 REG_SET(OPTC_MEMORY_CONFIG, 0,
285 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1);
329 REG_SET(OTG_GLOBAL_CONTROL0, 0,
332 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
335 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
348 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
351 REG_SET(OTG_VUPDATE_KEEPOUT, 0
[all...] |
| amdgpu_dcn20_hubp.c | 70 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
73 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
76 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
96 REG_SET(BLANK_OFFSET_1, 0,
99 REG_SET(DST_DIMENSIONS, 0,
106 REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
110 REG_SET(VBLANK_PARAMETERS_1, 0,
114 REG_SET(NOM_PARAMETERS_0, 0,
118 REG_SET(NOM_PARAMETERS_1, 0,
121 REG_SET(NOM_PARAMETERS_4, 0
[all...] |
| amdgpu_dcn20_dpp_cm.c | 104 REG_SET(CM_DGAM_LUT_INDEX, 0, CM_DGAM_LUT_INDEX, 0);
106 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].red_reg);
107 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].green_reg);
108 REG_SET(CM_DGAM_LUT_DATA, 0, CM_DGAM_LUT_DATA, rgb[i].blue_reg);
110 REG_SET(CM_DGAM_LUT_DATA, 0,
112 REG_SET(CM_DGAM_LUT_DATA, 0,
114 REG_SET(CM_DGAM_LUT_DATA, 0,
175 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
212 REG_SET(
257 REG_SET(CM_ICSC_CONTROL, 0, CM_ICSC_MODE, 0)
[all...] |
| amdgpu_dcn20_hubbub.c | 378 REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
380 REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
382 REG_SET(DCN_VM_FB_OFFSET, 0,
384 REG_SET(DCN_VM_AGP_BOT, 0,
386 REG_SET(DCN_VM_AGP_TOP, 0,
388 REG_SET(DCN_VM_AGP_BASE, 0,
391 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
393 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
595 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_mpc.c | 66 REG_SET(MPCC_BG_R_CR[bottommost_mpcc->mpcc_id], 0,
68 REG_SET(MPCC_BG_G_Y[bottommost_mpcc->mpcc_id], 0,
70 REG_SET(MPCC_BG_B_CB[bottommost_mpcc->mpcc_id], 0,
221 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, insert_above_mpcc->mpcc_id);
225 REG_SET(MPCC_BOT_SEL[mpcc_id], 0, MPCC_BOT_SEL, 0xf);
228 REG_SET(MPCC_TOP_SEL[mpcc_id], 0, MPCC_TOP_SEL, dpp_id);
229 REG_SET(MPCC_OPP_ID[mpcc_id], 0, MPCC_OPP_ID, tree->opp_id);
243 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0, MPCC_BOT_SEL, mpcc_id);
309 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0,
313 REG_SET(MPCC_BOT_SEL[temp_mpcc->mpcc_id], 0
[all...] |
| amdgpu_dcn10_hubp.c | 389 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
393 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
398 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
402 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
418 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
422 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
426 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
430 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
435 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
439 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0
[all...] |
| amdgpu_dcn10_dpp_cm.c | 105 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
159 REG_SET(
206 REG_SET(CM_TEST_DEBUG_INDEX, 0,
240 REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
328 REG_SET(CM_MEM_PWR_CTRL, 0,
343 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
344 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
345 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
347 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
348 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].delta_green_reg)
[all...] |
| amdgpu_dcn10_optc.c | 84 REG_SET(OTG_VSTARTUP_PARAM, 0,
91 REG_SET(OTG_VREADY_PARAM, 0,
99 REG_SET(OTG_STEREO_CONTROL, 0,
125 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
135 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
177 REG_SET(OTG_H_TOTAL, 0,
208 REG_SET(OTG_V_TOTAL, 0,
214 REG_SET(OTG_V_TOTAL_MAX, 0,
216 REG_SET(OTG_V_TOTAL_MIN, 0,
606 REG_SET(OTG_GLOBAL_CONTROL0, 0
[all...] |
| amdgpu_dcn10_hubbub.c | 323 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, 0,
346 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, 0,
369 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, 0,
392 REG_SET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, 0,
428 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, 0,
442 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, 0,
457 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, 0,
471 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, 0,
486 REG_SET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, 0,
500 REG_SET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, 0
[all...] |
| amdgpu_dcn10_opp.c | 103 REG_SET(FMT_DITHER_RAND_R_SEED, 0,
106 REG_SET(FMT_DITHER_RAND_G_SEED, 0,
109 REG_SET(FMT_DITHER_RAND_B_SEED, 0,
|
| amdgpu_dcn10_cm_common.c | 88 REG_SET(reg->start_slope_cntl_b, 0,
90 REG_SET(reg->start_slope_cntl_g, 0,
92 REG_SET(reg->start_slope_cntl_r, 0,
95 REG_SET(reg->start_end_cntl1_b, 0,
101 REG_SET(reg->start_end_cntl1_g, 0,
107 REG_SET(reg->start_end_cntl1_r, 0,
|
| amdgpu_dcn10_dpp.c | 130 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
262 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
398 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
|
| amdgpu_dcn10_dpp_dscl.c | 588 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
591 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
594 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0,
597 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_ipp.c | 134 REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0,
137 REG_SET(CUR_SURFACE_ADDRESS, 0,
185 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
188 REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7);
200 REG_SET(DC_LUT_RW_INDEX, 0,
204 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
207 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
210 REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
217 REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
|
| amdgpu_dce_transform.c | 125 REG_SET(SCL_BYPASS_CONTROL, 0, SCL_BYPASS_MODE, 0);
149 REG_SET(SCL_CONTROL, 0, SCL_BOUNDARY_MODE, 1);
204 REG_SET(DCFE_MEM_PWR_CTRL, power_ctl, SCL_COEFF_MEM_PWR_DIS, 1);
292 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0,
295 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0,
363 REG_SET(SCL_VERT_FILTER_CONTROL, 0,
378 REG_SET(SCL_HORZ_FILTER_CONTROL, 0,
543 REG_SET(OUT_ROUND_CONTROL, 0, OUT_ROUND_TRUNC_MODE, depth_bits);
749 REG_SET(DENORM_CONTROL, 0, DENORM_MODE, denorm_mode);
829 REG_SET(GAMUT_REMAP_CONTROL, 0, GRPH_GAMUT_REMAP_MODE, 1)
[all...] |
| amdgpu_dce_mem_input.c | 418 REG_SET(GRPH_X_START, 0,
421 REG_SET(GRPH_Y_START, 0,
424 REG_SET(GRPH_X_END, 0,
427 REG_SET(GRPH_Y_END, 0,
430 REG_SET(GRPH_PITCH, 0,
433 REG_SET(HW_ROTATION, 0,
599 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,
636 REG_SET(DMIF_BUFFER_CONTROL, dmif_buffer_control,
658 REG_SET(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
672 REG_SET(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0
[all...] |
| amdgpu_dce_aux.c | 250 value = REG_SET(AUX_SW_DATA, value,
254 value = REG_SET(AUX_SW_DATA, value,
267 value = REG_SET(AUX_SW_DATA, value,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_hubp.c | 91 REG_SET(VBLANK_PARAMETERS_5, 0,
98 REG_SET(VBLANK_PARAMETERS_6, 0,
103 REG_SET(FLIP_PARAMETERS_3, 0,
108 REG_SET(FLIP_PARAMETERS_4, 0,
111 REG_SET(FLIP_PARAMETERS_5, 0,
113 REG_SET(FLIP_PARAMETERS_6, 0,
344 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
347 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
720 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
724 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0
[all...] |
| amdgpu_dcn21_hubbub.c | 121 REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
123 REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
125 REG_SET(DCN_VM_FB_OFFSET, 0,
127 REG_SET(DCN_VM_AGP_BOT, 0,
129 REG_SET(DCN_VM_AGP_TOP, 0,
131 REG_SET(DCN_VM_AGP_BASE, 0,
178 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, 0,
186 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A, 0,
193 REG_SET(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A, 0,
216 REG_SET(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, 0
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/ |
| amdgpu_hw_ddc.c | 124 REG_SET(gpio.MASK_reg, regval,
133 REG_SET(gpio.MASK_reg, regval,
169 REG_SET(gpio.MASK_reg, regval,
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| r300d.h | 63 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
64 REG_SET(PACKET0_COUNT, (n)))
65 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
67 REG_SET(PACKET3_IT_OPCODE, (op)) | \
68 REG_SET(PACKET3_COUNT, (n)))
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| dmub_reg.h | 63 #define REG_SET(reg_name, initial_val, field, val) \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| reg_helper.h | 47 #ifdef REG_SET
48 #undef REG_SET
65 #define REG_SET(reg_name, initial_val, field, val) \
386 REG_SET(reg, val, f2, v2); }
390 val = REG_SET(reg, val, f2, v2); \
391 REG_SET(reg, val, f3, v3); }
|
