| /src/sys/external/bsd/drm2/dist/drm/amd/display/dmub/src/ |
| amdgpu_dmub_dcn20.c | 88 REG_WRITE(DMCUB_INBOX1_RPTR, 0);
89 REG_WRITE(DMCUB_INBOX1_WPTR, 0);
95 REG_WRITE(DMCUB_SCRATCH15, dmub->psp_version & 0x001100FF);
115 REG_WRITE(DMCUB_REGION3_CW0_OFFSET, offset.u.low_part);
116 REG_WRITE(DMCUB_REGION3_CW0_OFFSET_HIGH, offset.u.high_part);
117 REG_WRITE(DMCUB_REGION3_CW0_BASE_ADDRESS, cw0->region.base);
124 REG_WRITE(DMCUB_REGION3_CW1_OFFSET, offset.u.low_part);
125 REG_WRITE(DMCUB_REGION3_CW1_OFFSET_HIGH, offset.u.high_part);
126 REG_WRITE(DMCUB_REGION3_CW1_BASE_ADDRESS, cw1->region.base);
149 REG_WRITE(DMCUB_REGION3_CW2_OFFSET, offset.u.low_part)
[all...] |
| dmub_reg.h | 55 #define REG_WRITE(reg, val) \
56 ((CTX)->funcs.reg_write((CTX)->user_ctx, REG(reg), (val)))
|
| /src/sys/dev/goldfish/ |
| gfpic.c | 56 #define REG_WRITE(sc, r, v) \
69 REG_WRITE(sc, GFPIC_DISABLE_ALL, 0);
82 REG_WRITE(sc, GFPIC_ENABLE, (1U << pirq));
95 REG_WRITE(sc, GFPIC_DISABLE, (1U << pirq));
|
| gftty.c | 79 #define REG_WRITE(sc, r, v) REG_WRITE0((sc)->sc_config, (r), (v))
313 REG_WRITE(sc, GFTTY_CMD, CMD_READ_BUFFER);
346 REG_WRITE(sc, GFTTY_CMD, CMD_INT_DISABLE);
357 REG_WRITE(sc, GFTTY_CMD, CMD_READ_BUFFER);
390 REG_WRITE(sc, GFTTY_CMD, CMD_INT_ENABLE);
471 REG_WRITE(sc, GFTTY_CMD, CMD_INT_ENABLE);
487 REG_WRITE(sc, GFTTY_CMD, CMD_INT_DISABLE);
527 REG_WRITE(sc, GFTTY_CMD, CMD_INT_DISABLE);
653 REG_WRITE(sc, GFTTY_CMD, CMD_WRITE_BUFFER);
|
| /src/sys/arch/virt68k/dev/ |
| virtctrl.c | 66 #define REG_WRITE(sc, r, v) \
79 REG_WRITE(sc, VIRTCTRL_REG_CMD, CMD_PANIC);
81 REG_WRITE(sc, VIRTCTRL_REG_CMD, CMD_HALT);
83 REG_WRITE(sc, VIRTCTRL_REG_CMD, CMD_RESET);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/ |
| amdgpu_dce_abm.c | 75 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary);
233 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp);
249 REG_WRITE(BIOS_SCRATCH_2, s2);
261 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x103);
262 REG_WRITE(DC_ABM1_HG_SAMPLE_RATE, 0x101);
263 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x103);
264 REG_WRITE(DC_ABM1_LS_SAMPLE_RATE, 0x101);
265 REG_WRITE(BL1_PWM_BL_UPDATE_SAMPLE_RATE, 0x101);
372 REG_WRITE(BL_PWM_CNTL,
374 REG_WRITE(BL_PWM_CNTL2
[all...] |
| amdgpu_dce_dmcu.c | 94 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
97 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
119 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
346 REG_WRITE(DMCU_IRAM_RD_CTRL, dmcu_version_offset);
368 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm);
404 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF);
407 REG_WRITE(MASTER_COMM_DATA_REG2, abm_gain_stepsize);
479 REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset);
482 REG_WRITE(DMCU_IRAM_WR_DATA, src[count]);
521 REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset)
[all...] |
| amdgpu_dce_stream_encoder.c | 129 REG_WRITE(AFMT_GENERIC_0, *content++);
130 REG_WRITE(AFMT_GENERIC_1, *content++);
131 REG_WRITE(AFMT_GENERIC_2, *content++);
132 REG_WRITE(AFMT_GENERIC_3, *content++);
133 REG_WRITE(AFMT_GENERIC_4, *content++);
134 REG_WRITE(AFMT_GENERIC_5, *content++);
135 REG_WRITE(AFMT_GENERIC_6, *content++);
136 REG_WRITE(AFMT_GENERIC_7, *content);
468 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
762 REG_WRITE(AFMT_AVI_INFO0, content[0])
[all...] |
| amdgpu_dce_opp.c | 301 REG_WRITE(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, 0);
303 REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, 0);
305 REG_WRITE(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, 0);
|
| amdgpu_dce_transform.c | 237 REG_WRITE(DCFE_MEM_PWR_CTRL, power_ctl);
306 REG_WRITE(SCL_AUTOMATIC_MODE_CONTROL, 0);
341 REG_WRITE(SCL_F_SHARP_CONTROL, 0);
1189 REG_WRITE(REGAMMA_LUT_INDEX, 0);
1194 REG_WRITE(REGAMMA_LUT_DATA, rgb->red_reg);
1195 REG_WRITE(REGAMMA_LUT_DATA, rgb->green_reg);
1196 REG_WRITE(REGAMMA_LUT_DATA, rgb->blue_reg);
1197 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_red_reg);
1198 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_green_reg);
1199 REG_WRITE(REGAMMA_LUT_DATA, rgb->delta_blue_reg)
[all...] |
| amdgpu_dce_hwseq.c | 88 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
|
| amdgpu_dce_aux.c | 139 REG_WRITE(AUX_CONTROL, value);
153 REG_WRITE(AUX_CONTROL, value);
|
| /src/sys/arch/mips/adm5120/ |
| adm5120_intr.c | 159 #define REG_WRITE(o,v) (REG_READ(o)) = (v)
181 REG_WRITE(ICU_DISABLE_REG, ICU_INT_MASK);
219 REG_WRITE(ICU_MODE_REG,
222 REG_WRITE(ICU_MODE_REG,
226 REG_WRITE(ICU_ENABLE_REG, irqmask);
257 REG_WRITE(ICU_DISABLE_REG, irqmask);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn10/ |
| amdgpu_rv1_clk_mgr_vbios_smu.c | 79 REG_WRITE(MP1_SMN_C2PMSG_91, 0);
82 REG_WRITE(MP1_SMN_C2PMSG_83, param);
85 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr_vbios_smu.c | 64 REG_WRITE(MP1_SMN_C2PMSG_91, 0);
67 REG_WRITE(MP1_SMN_C2PMSG_83, param);
70 REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
|
| /src/sys/arch/mips/adm5120/dev/ |
| if_admsw.c | 165 #define REG_WRITE(o, v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v))
224 REG_WRITE(SEND_HBADDR_REG, ADMSW_CDTXHADDR(sc, 0));
225 REG_WRITE(SEND_LBADDR_REG, ADMSW_CDTXLADDR(sc, 0));
226 REG_WRITE(RECV_HBADDR_REG, ADMSW_CDRXHADDR(sc, 0));
227 REG_WRITE(RECV_LBADDR_REG, ADMSW_CDRXLADDR(sc, 0));
242 REG_WRITE(VLAN_G1_REG, i);
244 REG_WRITE(VLAN_G2_REG, i);
253 REG_WRITE(PORT_CONF0_REG,
255 REG_WRITE(CPUP_CONF_REG,
266 REG_WRITE(PHY_CNTL2_REG
[all...] |
| ahci.c | 245 #define REG_WRITE(o,v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v))
291 REG_WRITE(ADMHCD_REG_INTENABLE, 0); /* disable interrupts */
292 REG_WRITE(ADMHCD_REG_CONTROL, ADMHCD_SW_RESET); /* reset */
297 REG_WRITE(ADMHCD_REG_CONTROL, ADMHCD_HOST_EN);
298 REG_WRITE(ADMHCD_REG_HOSTHEAD, 0x00000000);
299 REG_WRITE(ADMHCD_REG_FMINTERVAL, 0x20002edf);
300 REG_WRITE(ADMHCD_REG_LSTHRESH, 0x628);
301 REG_WRITE(ADMHCD_REG_RHDESCR, ADMHCD_NPS | ADMHCD_LPSC);
302 REG_WRITE(ADMHCD_REG_HOSTCONTROL, ADMHCD_STATE_OP);
304 REG_WRITE(ADMHCD_REG_INTENABLE, 0); /* XXX: enable interrupts *
[all...] |
| uart.c | 55 #define REG_WRITE(o,v) bus_space_write_4(sc->sc_st, sc->sc_ioh, (o),(v))
145 REG_WRITE(UART_CR_REG,UART_CR_PORT_EN|UART_CR_RX_INT_EN|UART_CR_RX_TIMEOUT_INT_EN);
340 REG_WRITE(UART_ECR_REG, UART_ECR_RSR);
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/ |
| amdgpu_dcn20_opp.c | 267 REG_WRITE(DPG_CONTROL, 0);
268 REG_WRITE(DPG_COLOUR_R_CR, 0);
269 REG_WRITE(DPG_COLOUR_G_Y, 0);
270 REG_WRITE(DPG_COLOUR_B_CB, 0);
271 REG_WRITE(DPG_RAMP_CONTROL, 0);
|
| amdgpu_dcn20_stream_encoder.c | 262 REG_WRITE(AFMT_GENERIC_0, *content++);
263 REG_WRITE(AFMT_GENERIC_1, *content++);
264 REG_WRITE(AFMT_GENERIC_2, *content++);
265 REG_WRITE(AFMT_GENERIC_3, *content++);
266 REG_WRITE(AFMT_GENERIC_4, *content++);
267 REG_WRITE(AFMT_GENERIC_5, *content++);
268 REG_WRITE(AFMT_GENERIC_6, *content++);
269 REG_WRITE(AFMT_GENERIC_7, *content++);
|
| amdgpu_dcn20_hwseq.c | 237 REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
246 REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
249 REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
255 REG_WRITE(D1VGA_CONTROL, 0);
256 REG_WRITE(D2VGA_CONTROL, 0);
257 REG_WRITE(D3VGA_CONTROL, 0);
258 REG_WRITE(D4VGA_CONTROL, 0);
259 REG_WRITE(D5VGA_CONTROL, 0);
260 REG_WRITE(D6VGA_CONTROL, 0);
2307 REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_stream_encoder.c | 116 REG_WRITE(AFMT_GENERIC_0, *content++);
117 REG_WRITE(AFMT_GENERIC_1, *content++);
118 REG_WRITE(AFMT_GENERIC_2, *content++);
119 REG_WRITE(AFMT_GENERIC_3, *content++);
120 REG_WRITE(AFMT_GENERIC_4, *content++);
121 REG_WRITE(AFMT_GENERIC_5, *content++);
122 REG_WRITE(AFMT_GENERIC_6, *content++);
123 REG_WRITE(AFMT_GENERIC_7, *content);
428 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
816 REG_WRITE(AFMT_GENERIC_0, *content++)
[all...] |
| amdgpu_dcn10_optc.c | 674 REG_WRITE(OTG_TRIGA_CNTL, 0);
1021 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1145 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1148 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1159 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1160 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1161 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1398 REG_WRITE(OTG_CRC_CNTL, 0);
|
| amdgpu_dcn10_hubbub.c | 250 REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub1->debug_test_index_pstate);
335 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A, prog_wm_value);
358 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B, prog_wm_value);
381 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C, prog_wm_value);
404 REG_WRITE(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D, prog_wm_value);
|
| /src/sys/external/isc/atheros_hal/dist/ar5312/ |
| ar5312reg.h | 31 #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val);
|
