1 /* $NetBSD: cpu_subr.c,v 1.112 2026/01/09 22:54:33 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Matt Thomas. 5 * Copyright (c) 2001 Tsubai Masanari. 6 * Copyright (c) 1998, 1999, 2001 Internet Research Institute, Inc. 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by 20 * Internet Research Institute, Inc. 21 * 4. The name of the author may not be used to endorse or promote products 22 * derived from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 26 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: cpu_subr.c,v 1.112 2026/01/09 22:54:33 jmcneill Exp $"); 38 39 #include "sysmon_envsys.h" 40 41 #ifdef _KERNEL_OPT 42 #include "opt_altivec.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_ppcarch.h" 45 #include "opt_ppccache.h" 46 #include "opt_ppcparam.h" 47 #endif 48 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/device.h> 52 #include <sys/types.h> 53 #include <sys/lwp.h> 54 #include <sys/xcall.h> 55 56 #include <uvm/uvm.h> 57 58 #include <powerpc/pcb.h> 59 #include <powerpc/psl.h> 60 #include <powerpc/spr.h> 61 #include <powerpc/oea/hid.h> 62 #include <powerpc/oea/hid_601.h> 63 #include <powerpc/oea/spr.h> 64 #include <powerpc/oea/cpufeat.h> 65 66 #include <dev/sysmon/sysmonvar.h> 67 68 static void cpu_enable_l2cr(register_t); 69 static void cpu_enable_l3cr(register_t); 70 static void cpu_config_l2cr(int); 71 static void cpu_config_l3cr(int); 72 static void cpu_probe_speed(struct cpu_info *); 73 static void cpu_idlespin(void); 74 static void cpu_set_dfs_xcall(void *, void *); 75 #if NSYSMON_ENVSYS > 0 76 static void cpu_tau_setup(struct cpu_info *); 77 static void cpu_tau_refresh(struct sysmon_envsys *, envsys_data_t *); 78 #endif 79 80 extern void init_scom_speedctl(void); 81 82 int cpu = -1; 83 int ncpus; 84 85 struct fmttab { 86 register_t fmt_mask; 87 register_t fmt_value; 88 const char *fmt_string; 89 }; 90 91 /* 92 * This should be one per CPU but since we only support it on 750 variants it 93 * doesn't really matter since none of them support SMP 94 */ 95 envsys_data_t sensor; 96 97 static const struct fmttab cpu_7450_l2cr_formats[] = { 98 { L2CR_L2E, 0, " disabled" }, 99 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 100 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 101 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 102 { L2CR_L2E, ~0, " 256KB L2 cache" }, 103 { L2CR_L2PE, 0, " no parity" }, 104 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 105 { 0, 0, NULL } 106 }; 107 108 static const struct fmttab cpu_7448_l2cr_formats[] = { 109 { L2CR_L2E, 0, " disabled" }, 110 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 111 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 112 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 113 { L2CR_L2E, ~0, " 1MB L2 cache" }, 114 { L2CR_L2PE, 0, " no parity" }, 115 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 116 { 0, 0, NULL } 117 }; 118 119 static const struct fmttab cpu_7457_l2cr_formats[] = { 120 { L2CR_L2E, 0, " disabled" }, 121 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 122 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 123 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 124 { L2CR_L2E, ~0, " 512KB L2 cache" }, 125 { L2CR_L2PE, 0, " no parity" }, 126 { L2CR_L2PE, L2CR_L2PE, " parity enabled" }, 127 { 0, 0, NULL } 128 }; 129 130 static const struct fmttab cpu_7450_l3cr_formats[] = { 131 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO, " data-only" }, 132 { L3CR_L3DO|L3CR_L3IO, L3CR_L3IO, " instruction-only" }, 133 { L3CR_L3DO|L3CR_L3IO, L3CR_L3DO|L3CR_L3IO, " locked" }, 134 { L3CR_L3SIZ, L3SIZ_2M, " 2MB" }, 135 { L3CR_L3SIZ, L3SIZ_1M, " 1MB" }, 136 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE|L3CR_L3APE, " parity" }, 137 { L3CR_L3PE|L3CR_L3APE, L3CR_L3PE, " data-parity" }, 138 { L3CR_L3PE|L3CR_L3APE, L3CR_L3APE, " address-parity" }, 139 { L3CR_L3PE|L3CR_L3APE, 0, " no-parity" }, 140 { L3CR_L3SIZ, ~0, " L3 cache" }, 141 { L3CR_L3RT, L3RT_MSUG2_DDR, " (DDR SRAM)" }, 142 { L3CR_L3RT, L3RT_PIPELINE_LATE, " (LW SRAM)" }, 143 { L3CR_L3RT, L3RT_PB2_SRAM, " (PB2 SRAM)" }, 144 { L3CR_L3CLK, ~0, " at" }, 145 { L3CR_L3CLK, L3CLK_20, " 2:1" }, 146 { L3CR_L3CLK, L3CLK_25, " 2.5:1" }, 147 { L3CR_L3CLK, L3CLK_30, " 3:1" }, 148 { L3CR_L3CLK, L3CLK_35, " 3.5:1" }, 149 { L3CR_L3CLK, L3CLK_40, " 4:1" }, 150 { L3CR_L3CLK, L3CLK_50, " 5:1" }, 151 { L3CR_L3CLK, L3CLK_60, " 6:1" }, 152 { L3CR_L3CLK, ~0, " ratio" }, 153 { 0, 0, NULL }, 154 }; 155 156 static const struct fmttab cpu_ibm750cl_l2cr_formats[] = { 157 { L2CR_L2E, 0, " disabled" }, 158 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 159 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 160 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 161 { 0, ~0, " 256KB" }, 162 { L2CR_L2WT, L2CR_L2WT, " WT" }, 163 { L2CR_L2WT, 0, " WB" }, 164 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 165 { 0, ~0, " L2 cache" }, 166 { 0, 0, NULL } 167 }; 168 169 static const struct fmttab cpu_ibm750_l2cr_formats[] = { 170 { L2CR_L2E, 0, " disabled" }, 171 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 172 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 173 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 174 { 0, ~0, " 512KB" }, 175 { L2CR_L2WT, L2CR_L2WT, " WT" }, 176 { L2CR_L2WT, 0, " WB" }, 177 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 178 { 0, ~0, " L2 cache" }, 179 { 0, 0, NULL } 180 }; 181 182 static const struct fmttab cpu_espresso_l2cr_formats[] = { 183 { L2CR_L2E, 0, " disabled" }, 184 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 185 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 186 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 187 { L2SIZ_512K, 0, " 512KB" }, 188 { L2SIZ_512K, L2SIZ_512K, " 2MB" }, 189 { L2CR_L2WT, L2CR_L2WT, " WT" }, 190 { L2CR_L2WT, 0, " WB" }, 191 { L2CR_L2PE, L2CR_L2PE, " with ECC" }, 192 { 0, ~0, " L2 cache" }, 193 { 0, 0, NULL } 194 }; 195 196 static const struct fmttab cpu_l2cr_formats[] = { 197 { L2CR_L2E, 0, " disabled" }, 198 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO, " data-only" }, 199 { L2CR_L2DO|L2CR_L2IO, L2CR_L2IO, " instruction-only" }, 200 { L2CR_L2DO|L2CR_L2IO, L2CR_L2DO|L2CR_L2IO, " locked" }, 201 { L2CR_L2PE, L2CR_L2PE, " parity" }, 202 { L2CR_L2PE, 0, " no-parity" }, 203 { L2CR_L2SIZ, L2SIZ_2M, " 2MB" }, 204 { L2CR_L2SIZ, L2SIZ_1M, " 1MB" }, 205 { L2CR_L2SIZ, L2SIZ_512K, " 512KB" }, 206 { L2CR_L2SIZ, L2SIZ_256K, " 256KB" }, 207 { L2CR_L2WT, L2CR_L2WT, " WT" }, 208 { L2CR_L2WT, 0, " WB" }, 209 { L2CR_L2E, ~0, " L2 cache" }, 210 { L2CR_L2RAM, L2RAM_FLOWTHRU_BURST, " (FB SRAM)" }, 211 { L2CR_L2RAM, L2RAM_PIPELINE_LATE, " (LW SRAM)" }, 212 { L2CR_L2RAM, L2RAM_PIPELINE_BURST, " (PB SRAM)" }, 213 { L2CR_L2CLK, ~0, " at" }, 214 { L2CR_L2CLK, L2CLK_10, " 1:1" }, 215 { L2CR_L2CLK, L2CLK_15, " 1.5:1" }, 216 { L2CR_L2CLK, L2CLK_20, " 2:1" }, 217 { L2CR_L2CLK, L2CLK_25, " 2.5:1" }, 218 { L2CR_L2CLK, L2CLK_30, " 3:1" }, 219 { L2CR_L2CLK, L2CLK_35, " 3.5:1" }, 220 { L2CR_L2CLK, L2CLK_40, " 4:1" }, 221 { L2CR_L2CLK, ~0, " ratio" }, 222 { 0, 0, NULL } 223 }; 224 225 static void cpu_fmttab_print(const struct fmttab *, register_t); 226 227 struct cputab { 228 const char name[9]; 229 uint16_t version; 230 uint16_t revfmt; 231 }; 232 #define REVFMT_MAJMIN 1 /* %u.%u */ 233 #define REVFMT_HEX 2 /* 0x%04x */ 234 #define REVFMT_DEC 3 /* %u */ 235 static const struct cputab models[] = { 236 { "601", MPC601, REVFMT_DEC }, 237 { "602", MPC602, REVFMT_DEC }, 238 { "603", MPC603, REVFMT_MAJMIN }, 239 { "603e", MPC603e, REVFMT_MAJMIN }, 240 { "603ev", MPC603ev, REVFMT_MAJMIN }, 241 { "G2", MPCG2, REVFMT_MAJMIN }, 242 { "604", MPC604, REVFMT_MAJMIN }, 243 { "604e", MPC604e, REVFMT_MAJMIN }, 244 { "604ev", MPC604ev, REVFMT_MAJMIN }, 245 { "620", MPC620, REVFMT_HEX }, 246 { "750", MPC750, REVFMT_MAJMIN }, 247 { "750FX", IBM750FX, REVFMT_MAJMIN }, 248 { "750GX", IBM750GX, REVFMT_MAJMIN }, 249 { "7400", MPC7400, REVFMT_MAJMIN }, 250 { "7410", MPC7410, REVFMT_MAJMIN }, 251 { "7450", MPC7450, REVFMT_MAJMIN }, 252 { "7455", MPC7455, REVFMT_MAJMIN }, 253 { "7457", MPC7457, REVFMT_MAJMIN }, 254 { "7447A", MPC7447A, REVFMT_MAJMIN }, 255 { "7448", MPC7448, REVFMT_MAJMIN }, 256 { "8240", MPC8240, REVFMT_MAJMIN }, 257 { "8245", MPC8245, REVFMT_MAJMIN }, 258 { "970", IBM970, REVFMT_MAJMIN }, 259 { "970FX", IBM970FX, REVFMT_MAJMIN }, 260 { "970MP", IBM970MP, REVFMT_MAJMIN }, 261 { "POWER3II", IBMPOWER3II, REVFMT_MAJMIN }, 262 { "Espresso", IBMESPRESSO, REVFMT_MAJMIN }, 263 { "", 0, REVFMT_HEX } 264 }; 265 266 #include <powerpc/oea/bat.h> 267 extern struct bat battable[]; 268 269 #ifdef MULTIPROCESSOR 270 struct cpu_info cpu_info[CPU_MAXNUM] = { 271 [0] = { 272 .ci_curlwp = &lwp0, 273 .ci_battable = battable, 274 }, 275 }; 276 volatile struct cpu_hatch_data *cpu_hatch_data; 277 volatile int cpu_hatch_stack; 278 #define HATCH_STACK_SIZE 0x1000 279 extern int ticks_per_intr; 280 #include <powerpc/pic/picvar.h> 281 #include <powerpc/pic/ipivar.h> 282 #else 283 struct cpu_info cpu_info[1] = { 284 [0] = { 285 .ci_curlwp = &lwp0, 286 .ci_battable = battable, 287 }, 288 }; 289 #endif /*MULTIPROCESSOR*/ 290 291 int cpu_altivec; 292 register_t cpu_psluserset; 293 register_t cpu_pslusermod; 294 register_t cpu_pslusermask = 0xffff; 295 296 unsigned long oeacpufeat; 297 298 void 299 cpu_features_probe(void) 300 { 301 static bool feature_probe_done; 302 303 u_int pvr, vers; 304 305 if (feature_probe_done) { 306 return; 307 } 308 309 pvr = mfpvr(); 310 vers = pvr >> 16; 311 312 if ((vers >= IBMRS64II && vers <= IBM970GX) || vers == MPC620 || 313 vers == IBMCELL || vers == IBMPOWER6P5) { 314 oeacpufeat |= OEACPU_64; 315 oeacpufeat |= OEACPU_64_BRIDGE; 316 oeacpufeat |= OEACPU_NOBAT; 317 318 } else if (vers == MPC601) { 319 oeacpufeat |= OEACPU_601; 320 321 } else if (MPC745X_P(vers)) { 322 if (vers != MPC7450) { 323 /* Enable more SPRG registers */ 324 oeacpufeat |= OEACPU_HIGHSPRG; 325 326 /* Enable more BAT registers */ 327 oeacpufeat |= OEACPU_HIGHBAT; 328 329 /* Enable larger BAT registers */ 330 oeacpufeat |= OEACPU_XBSEN; 331 } 332 333 } else if (vers == IBMESPRESSO) { 334 oeacpufeat |= OEACPU_HIGHBAT; 335 336 } else if (vers == IBM750FX || vers == IBM750GX) { 337 oeacpufeat |= OEACPU_HIGHBAT; 338 } 339 340 feature_probe_done = true; 341 } 342 343 void 344 cpu_features_enable(void) 345 { 346 static bool feature_enable_done; 347 348 if (feature_enable_done) { 349 return; 350 } 351 352 u_int pvr, vers; 353 354 pvr = mfpvr(); 355 vers = pvr >> 16; 356 357 if (MPC745X_P(vers)) { 358 register_t hid0 = mfspr(SPR_HID0); 359 register_t hid1 = mfspr(SPR_HID1); 360 361 const register_t ohid0 = hid0; 362 363 if (oeacpufeat & OEACPU_HIGHBAT) { 364 hid0 |= HID0_HIGH_BAT_EN; 365 } 366 367 if (oeacpufeat & OEACPU_XBSEN) { 368 hid0 |= HID0_XBSEN; 369 } 370 371 if (hid0 != ohid0) { 372 mtspr(SPR_HID0, hid0); 373 __asm volatile("sync;isync"); 374 } 375 376 /* Enable address broadcasting for MP systems */ 377 hid1 |= HID1_SYNCBE | HID1_ABE; 378 379 mtspr(SPR_HID1, hid1); 380 __asm volatile("sync;isync"); 381 } else if (vers == IBMESPRESSO) { 382 register_t spr; 383 384 spr = mfspr(SPR_IBMESPRESSO_HID4); 385 mtspr(SPR_IBMESPRESSO_HID4, spr | HID4_H4A | HID4_SBE); 386 387 spr = mfspr(SPR_HID0); 388 mtspr(SPR_HID0, spr | HID0_ABE); 389 390 __asm volatile("sync;isync"); 391 } 392 393 394 feature_enable_done = true; 395 } 396 397 /* This is to be called from locore.S, and nowhere else. */ 398 399 void 400 cpu_model_init(void) 401 { 402 /* 403 * This is just a wrapper for backwards-compatibility, and will 404 * probably be garbage-collected in the near future. 405 */ 406 cpu_features_probe(); 407 cpu_features_enable(); 408 } 409 410 void 411 cpu_fmttab_print(const struct fmttab *fmt, register_t data) 412 { 413 for (; fmt->fmt_mask != 0 || fmt->fmt_value != 0; fmt++) { 414 if ((~fmt->fmt_mask & fmt->fmt_value) != 0 || 415 (data & fmt->fmt_mask) == fmt->fmt_value) 416 aprint_normal("%s", fmt->fmt_string); 417 } 418 } 419 420 void 421 cpu_idlespin(void) 422 { 423 register_t msr; 424 425 if (powersave <= 0) 426 return; 427 428 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 429 if (cpu_altivec) 430 __asm volatile("dssall"); 431 #endif 432 433 __asm volatile( 434 "sync;" 435 "mfmsr %0;" 436 "oris %0,%0,%1@h;" /* enter power saving mode */ 437 "mtmsr %0;" 438 "isync;" 439 : "=r"(msr) 440 : "J"(PSL_POW)); 441 } 442 443 void 444 cpu_probe_cache(void) 445 { 446 u_int assoc, pvr, vers; 447 448 pvr = mfpvr(); 449 vers = pvr >> 16; 450 451 452 /* Presently common across almost all implementations. */ 453 curcpu()->ci_ci.dcache_line_size = 32; 454 curcpu()->ci_ci.icache_line_size = 32; 455 456 457 switch (vers) { 458 #define K *1024 459 case IBM750FX: 460 case IBM750GX: 461 case IBMESPRESSO: 462 case MPC601: 463 case MPC750: 464 case MPC7400: 465 case MPC7447A: 466 case MPC7448: 467 case MPC7450: 468 case MPC7455: 469 case MPC7457: 470 curcpu()->ci_ci.dcache_size = 32 K; 471 curcpu()->ci_ci.icache_size = 32 K; 472 assoc = 8; 473 break; 474 case MPC603: 475 curcpu()->ci_ci.dcache_size = 8 K; 476 curcpu()->ci_ci.icache_size = 8 K; 477 assoc = 2; 478 break; 479 case MPC603e: 480 case MPC603ev: 481 case MPC604: 482 case MPC8240: 483 case MPC8245: 484 case MPCG2: 485 curcpu()->ci_ci.dcache_size = 16 K; 486 curcpu()->ci_ci.icache_size = 16 K; 487 assoc = 4; 488 break; 489 case MPC604e: 490 case MPC604ev: 491 curcpu()->ci_ci.dcache_size = 32 K; 492 curcpu()->ci_ci.icache_size = 32 K; 493 assoc = 4; 494 break; 495 case IBMPOWER3II: 496 curcpu()->ci_ci.dcache_size = 64 K; 497 curcpu()->ci_ci.icache_size = 32 K; 498 curcpu()->ci_ci.dcache_line_size = 128; 499 curcpu()->ci_ci.icache_line_size = 128; 500 assoc = 128; /* not a typo */ 501 break; 502 case IBM970: 503 case IBM970FX: 504 case IBM970MP: 505 curcpu()->ci_ci.dcache_size = 32 K; 506 curcpu()->ci_ci.icache_size = 64 K; 507 curcpu()->ci_ci.dcache_line_size = 128; 508 curcpu()->ci_ci.icache_line_size = 128; 509 assoc = 2; 510 break; 511 512 default: 513 curcpu()->ci_ci.dcache_size = PAGE_SIZE; 514 curcpu()->ci_ci.icache_size = PAGE_SIZE; 515 assoc = 1; 516 #undef K 517 } 518 519 /* 520 * Possibly recolor. 521 */ 522 uvm_page_recolor(atop(curcpu()->ci_ci.dcache_size / assoc)); 523 } 524 525 struct cpu_info * 526 cpu_attach_common(device_t self, int id) 527 { 528 struct cpu_info *ci; 529 u_int pvr, vers; 530 531 ci = &cpu_info[id]; 532 #ifndef MULTIPROCESSOR 533 /* 534 * If this isn't the primary CPU, print an error message 535 * and just bail out. 536 */ 537 if (id != 0) { 538 aprint_naive("\n"); 539 aprint_normal(": ID %d\n", id); 540 aprint_normal_dev(self, 541 "processor off-line; " 542 "multiprocessor support not present in kernel\n"); 543 return (NULL); 544 } 545 #endif 546 547 ci->ci_cpuid = id; 548 ci->ci_idepth = -1; 549 ci->ci_dev = self; 550 ci->ci_idlespin = cpu_idlespin; 551 552 #ifdef MULTIPROCESSOR 553 /* Register IPI Interrupt */ 554 if ((ipiops.ppc_establish_ipi) && (id == 0)) 555 ipiops.ppc_establish_ipi(IST_LEVEL, IPL_HIGH, NULL); 556 #endif 557 558 pvr = mfpvr(); 559 vers = (pvr >> 16) & 0xffff; 560 561 switch (id) { 562 case 0: 563 /* load my cpu_number to PIR */ 564 switch (vers) { 565 case MPC601: 566 case MPC604: 567 case MPC604e: 568 case MPC604ev: 569 case MPC7400: 570 case MPC7410: 571 case MPC7447A: 572 case MPC7448: 573 case MPC7450: 574 case MPC7455: 575 case MPC7457: 576 mtspr(SPR_PIR, id); 577 } 578 cpu_setup(self, ci); 579 break; 580 default: 581 aprint_naive("\n"); 582 if (id >= CPU_MAXNUM) { 583 aprint_normal(": more than %d cpus?\n", CPU_MAXNUM); 584 panic("cpuattach"); 585 } 586 #ifndef MULTIPROCESSOR 587 aprint_normal(" not configured\n"); 588 return NULL; 589 #else 590 mi_cpu_attach(ci); 591 break; 592 #endif 593 } 594 return (ci); 595 } 596 597 void 598 cpu_setup(device_t self, struct cpu_info *ci) 599 { 600 u_int pvr, vers; 601 const char * const xname = device_xname(self); 602 const char *bitmask; 603 char hidbuf[128]; 604 char model[80]; 605 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 606 char hidbuf_u[128]; 607 const char *bitmasku = NULL; 608 volatile uint64_t hid64_0, hid64_0_save; 609 #endif 610 #if !defined(_ARCH_PPC64) 611 register_t hid0 = 0, hid0_save = 0; 612 #endif 613 614 pvr = mfpvr(); 615 vers = (pvr >> 16) & 0xffff; 616 617 cpu_identify(model, sizeof(model)); 618 aprint_naive("\n"); 619 aprint_normal(": %s, ID %d%s\n", model, cpu_number(), 620 cpu_number() == 0 ? " (primary)" : ""); 621 622 /* set the cpu number */ 623 ci->ci_cpuid = cpu_number(); 624 #if defined(_ARCH_PPC64) 625 __asm volatile("mfspr %0,%1" : "=r"(hid64_0) : "K"(SPR_HID0)); 626 hid64_0_save = hid64_0; 627 #else 628 #if defined(PPC_OEA64_BRIDGE) 629 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) 630 hid64_0_save = hid64_0 = mfspr(SPR_HID0); 631 else 632 #endif 633 hid0_save = hid0 = mfspr(SPR_HID0); 634 #endif 635 636 637 cpu_probe_cache(); 638 639 /* 640 * Configure power-saving mode. 641 */ 642 switch (vers) { 643 #if !defined(_ARCH_PPC64) 644 case MPC604: 645 case MPC604e: 646 case MPC604ev: 647 /* 648 * Do not have HID0 support settings, but can support 649 * MSR[POW] off 650 */ 651 powersave = 1; 652 break; 653 654 case MPC603: 655 case MPC603e: 656 case MPC603ev: 657 case MPC7400: 658 case MPC7410: 659 case MPC8240: 660 case MPC8245: 661 case MPCG2: 662 case IBMESPRESSO: 663 /* Select DOZE mode. */ 664 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 665 hid0 |= HID0_DOZE | HID0_DPM; 666 powersave = 1; 667 break; 668 669 case MPC750: 670 case IBM750FX: 671 case IBM750GX: 672 /* Select NAP mode. */ 673 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 674 hid0 |= HID0_NAP | HID0_DPM; 675 powersave = 1; 676 break; 677 678 case MPC7447A: 679 case MPC7448: 680 case MPC7457: 681 case MPC7455: 682 case MPC7450: 683 /* Enable the 7450 branch caches */ 684 hid0 |= HID0_SGE | HID0_BTIC; 685 hid0 |= HID0_LRSTK | HID0_FOLD | HID0_BHT; 686 /* Disable BTIC on 7450 Rev 2.0 or earlier */ 687 if (vers == MPC7450 && (pvr & 0xFFFF) <= 0x0200) 688 hid0 &= ~HID0_BTIC; 689 /* Select NAP mode. */ 690 hid0 &= ~HID0_SLEEP; 691 /* XXX my quicksilver hangs if nap is enabled */ 692 if (vers != MPC7450) { 693 hid0 |= HID0_NAP | HID0_DPM; 694 powersave = 1; 695 } 696 break; 697 #endif 698 699 case IBM970: 700 case IBM970FX: 701 case IBM970MP: 702 #if defined(_ARCH_PPC64) || defined (PPC_OEA64_BRIDGE) 703 #if !defined(_ARCH_PPC64) 704 KASSERT((oeacpufeat & OEACPU_64_BRIDGE) != 0); 705 #endif 706 hid64_0 &= ~(HID0_64_DOZE | HID0_64_NAP | HID0_64_DEEPNAP); 707 hid64_0 |= HID0_64_NAP | HID0_64_DPM | HID0_64_EX_TBEN | 708 HID0_64_TB_CTRL | HID0_64_EN_MCHK; 709 powersave = 1; 710 break; 711 #endif 712 case IBMPOWER3II: 713 default: 714 /* No power-saving mode is available. */ ; 715 } 716 717 #ifdef NAPMODE 718 switch (vers) { 719 case IBM750FX: 720 case IBM750GX: 721 case IBMESPRESSO: 722 case MPC750: 723 case MPC7400: 724 /* Select NAP mode. */ 725 hid0 &= ~(HID0_DOZE | HID0_NAP | HID0_SLEEP); 726 hid0 |= HID0_NAP; 727 break; 728 } 729 #endif 730 731 switch (vers) { 732 case IBM750FX: 733 case IBM750GX: 734 case MPC750: 735 hid0 &= ~HID0_DBP; /* XXX correct? */ 736 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 737 break; 738 739 case IBMESPRESSO: 740 hid0 |= HID0_DBP; 741 hid0 |= HID0_IFEM | HID0_ABE; 742 hid0 |= HID0_BTIC | HID0_BHT | HID0_NHR; 743 break; 744 745 case MPC7400: 746 case MPC7410: 747 hid0 &= ~HID0_SPD; 748 hid0 |= HID0_EMCP | HID0_BTIC | HID0_SGE | HID0_BHT; 749 hid0 |= HID0_EIEC; 750 break; 751 } 752 753 /* 754 * according to the 603e manual this is necessary for an external L2 755 * cache to work properly 756 */ 757 switch (vers) { 758 case MPC603e: 759 hid0 |= HID0_ABE; 760 } 761 762 #if defined(_ARCH_PPC64) || defined(PPC_OEA64_BRIDGE) 763 #if defined(PPC_OEA64_BRIDGE) 764 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 765 #endif 766 if (hid64_0 != hid64_0_save) { 767 mtspr64(SPR_HID0, hid64_0); 768 } 769 #if defined(PPC_OEA64_BRIDGE) 770 } else { 771 #endif 772 #endif 773 774 #if !defined(_ARCH_PPC64) 775 if (hid0 != hid0_save) { 776 mtspr(SPR_HID0, hid0); 777 __asm volatile("sync;isync"); 778 } 779 #endif 780 #if defined(PPC_OEA64_BRIDGE) 781 } 782 #endif 783 784 switch (vers) { 785 case MPC601: 786 bitmask = HID0_601_BITMASK; 787 break; 788 case MPC7447A: 789 case MPC7448: 790 case MPC7450: 791 case MPC7455: 792 case MPC7457: 793 bitmask = HID0_7450_BITMASK; 794 break; 795 case IBM970: 796 case IBM970FX: 797 case IBM970MP: 798 bitmask = HID0_970_BITMASK; 799 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 800 bitmasku = HID0_970_BITMASK_U; 801 #endif 802 break; 803 default: 804 bitmask = HID0_BITMASK; 805 break; 806 } 807 808 #if defined(PPC_OEA64_BRIDGE) || defined(_ARCH_PPC64) 809 if (bitmasku != NULL) { 810 snprintb(hidbuf, sizeof hidbuf, bitmask, hid64_0 & 0xffffffff); 811 snprintb(hidbuf_u, sizeof hidbuf_u, bitmasku, hid64_0 >> 32); 812 aprint_normal_dev(self, "HID0 %s %s, powersave: %d\n", 813 hidbuf_u, hidbuf, powersave); 814 } else 815 #endif 816 { 817 snprintb(hidbuf, sizeof hidbuf, bitmask, hid0); 818 aprint_normal_dev(self, "HID0 %s, powersave: %d\n", 819 hidbuf, powersave); 820 } 821 822 823 if (vers == IBMESPRESSO) { 824 register_t spr; 825 826 mtspr(SPR_IBMESPRESSO_HID2, 0); 827 828 spr = HID4_H4A | HID4_L2FM_64B | HID4_BPD_4 | 829 HID4_SBE | HID4_LPE | HID4_ST0 | HID4_DBP | 830 HID4_L2MUM | HID4_L2_CCFI; 831 mtspr(SPR_IBMESPRESSO_HID4, spr); 832 833 spr = mfspr(SPR_IBMESPRESSO_HID5); 834 mtspr(SPR_IBMESPRESSO_HID5, spr | 0x67fdc000); 835 836 spr = mfspr(SPR_IBMESPRESSO_HID4); 837 snprintb(hidbuf, sizeof hidbuf, IBM750CL_HID4_BITMASK, spr); 838 aprint_normal_dev(self, "HID4 %s\n", hidbuf); 839 840 spr = mfspr(SPR_IBMESPRESSO_HID5); 841 snprintb(hidbuf, sizeof hidbuf, IBMESPRESSO_HID5_BITMASK, spr); 842 aprint_normal_dev(self, "HID5 %s\n", hidbuf); 843 } 844 845 ci->ci_khz = 0; 846 847 /* 848 * Display speed and cache configuration. 849 */ 850 switch (vers) { 851 case MPC604: 852 case MPC604e: 853 case MPC604ev: 854 case MPC750: 855 case IBM750FX: 856 case IBM750GX: 857 case IBMESPRESSO: 858 case MPC7400: 859 case MPC7410: 860 case MPC7447A: 861 case MPC7448: 862 case MPC7450: 863 case MPC7455: 864 case MPC7457: 865 aprint_normal_dev(self, ""); 866 cpu_probe_speed(ci); 867 aprint_normal("%u.%02u MHz", 868 ci->ci_khz / 1000, (ci->ci_khz / 10) % 100); 869 switch (vers) { 870 case MPC7450: /* 7441 does not have L3! */ 871 case MPC7455: /* 7445 does not have L3! */ 872 case MPC7457: /* 7447 does not have L3! */ 873 cpu_config_l3cr(vers); 874 break; 875 case IBM750FX: 876 case IBM750GX: 877 case IBMESPRESSO: 878 case MPC750: 879 case MPC7400: 880 case MPC7410: 881 case MPC7447A: 882 case MPC7448: 883 cpu_config_l2cr(pvr); 884 break; 885 default: 886 break; 887 } 888 aprint_normal("\n"); 889 break; 890 } 891 892 #if NSYSMON_ENVSYS > 0 893 /* 894 * Attach MPC750 temperature sensor to the envsys subsystem. 895 * XXX the 74xx series also has this sensor, but it is not 896 * XXX supported by Motorola and may return values that are off by 897 * XXX 35-55 degrees C. 898 */ 899 if (vers == MPC750 || vers == IBM750FX || vers == IBM750GX) 900 cpu_tau_setup(ci); 901 #endif 902 903 #if defined(PPC_OEA64) || defined(PPC_OEA64_BRIDGE) 904 if (vers == IBM970MP) 905 init_scom_speedctl(); 906 #endif 907 908 evcnt_attach_dynamic(&ci->ci_ev_clock, EVCNT_TYPE_INTR, 909 NULL, xname, "clock"); 910 evcnt_attach_dynamic(&ci->ci_ev_traps, EVCNT_TYPE_TRAP, 911 NULL, xname, "traps"); 912 evcnt_attach_dynamic(&ci->ci_ev_kdsi, EVCNT_TYPE_TRAP, 913 &ci->ci_ev_traps, xname, "kernel DSI traps"); 914 evcnt_attach_dynamic(&ci->ci_ev_udsi, EVCNT_TYPE_TRAP, 915 &ci->ci_ev_traps, xname, "user DSI traps"); 916 evcnt_attach_dynamic(&ci->ci_ev_udsi_fatal, EVCNT_TYPE_TRAP, 917 &ci->ci_ev_udsi, xname, "user DSI failures"); 918 evcnt_attach_dynamic(&ci->ci_ev_kisi, EVCNT_TYPE_TRAP, 919 &ci->ci_ev_traps, xname, "kernel ISI traps"); 920 evcnt_attach_dynamic(&ci->ci_ev_isi, EVCNT_TYPE_TRAP, 921 &ci->ci_ev_traps, xname, "user ISI traps"); 922 evcnt_attach_dynamic(&ci->ci_ev_isi_fatal, EVCNT_TYPE_TRAP, 923 &ci->ci_ev_isi, xname, "user ISI failures"); 924 evcnt_attach_dynamic(&ci->ci_ev_scalls, EVCNT_TYPE_TRAP, 925 &ci->ci_ev_traps, xname, "system call traps"); 926 evcnt_attach_dynamic(&ci->ci_ev_pgm, EVCNT_TYPE_TRAP, 927 &ci->ci_ev_traps, xname, "PGM traps"); 928 evcnt_attach_dynamic(&ci->ci_ev_fpu, EVCNT_TYPE_TRAP, 929 &ci->ci_ev_traps, xname, "FPU unavailable traps"); 930 evcnt_attach_dynamic(&ci->ci_ev_fpusw, EVCNT_TYPE_TRAP, 931 &ci->ci_ev_fpu, xname, "FPU context switches"); 932 evcnt_attach_dynamic(&ci->ci_ev_ali, EVCNT_TYPE_TRAP, 933 &ci->ci_ev_traps, xname, "user alignment traps"); 934 evcnt_attach_dynamic(&ci->ci_ev_ali_fatal, EVCNT_TYPE_TRAP, 935 &ci->ci_ev_ali, xname, "user alignment failures"); 936 evcnt_attach_dynamic(&ci->ci_ev_umchk, EVCNT_TYPE_TRAP, 937 &ci->ci_ev_umchk, xname, "user MCHK failures"); 938 evcnt_attach_dynamic(&ci->ci_ev_vec, EVCNT_TYPE_TRAP, 939 &ci->ci_ev_traps, xname, "AltiVec unavailable"); 940 #ifdef ALTIVEC 941 if (cpu_altivec) { 942 evcnt_attach_dynamic(&ci->ci_ev_vecsw, EVCNT_TYPE_TRAP, 943 &ci->ci_ev_vec, xname, "AltiVec context switches"); 944 } 945 #endif 946 evcnt_attach_dynamic(&ci->ci_ev_ipi, EVCNT_TYPE_INTR, 947 NULL, xname, "IPIs"); 948 } 949 950 /* 951 * According to a document labeled "PVR Register Settings": 952 ** For integrated microprocessors the PVR register inside the device 953 ** will identify the version of the microprocessor core. You must also 954 ** read the Device ID, PCI register 02, to identify the part and the 955 ** Revision ID, PCI register 08, to identify the revision of the 956 ** integrated microprocessor. 957 * This apparently applies to 8240/8245/8241, PVR 00810101 and 80811014 958 */ 959 960 void 961 cpu_identify(char *str, size_t len) 962 { 963 u_int pvr, major, minor; 964 uint16_t vers, rev, revfmt; 965 const struct cputab *cp; 966 size_t n; 967 968 pvr = mfpvr(); 969 vers = pvr >> 16; 970 rev = pvr; 971 972 switch (vers) { 973 case MPC7410: 974 minor = (pvr >> 0) & 0xff; 975 major = minor <= 4 ? 1 : 2; 976 break; 977 case MPCG2: /*XXX see note above */ 978 major = (pvr >> 4) & 0xf; 979 minor = (pvr >> 0) & 0xf; 980 break; 981 default: 982 major = (pvr >> 8) & 0xf; 983 minor = (pvr >> 0) & 0xf; 984 } 985 986 for (cp = models; cp->name[0] != '\0'; cp++) { 987 if (cp->version == vers) 988 break; 989 } 990 991 if (cpu == -1) 992 cpu = vers; 993 994 revfmt = cp->revfmt; 995 if (rev == MPC750 && pvr == 15) { 996 revfmt = REVFMT_HEX; 997 } 998 if (vers == MPC750 && (pvr & 0xf000) == 0x7000 && 999 (pvr & 0x0f00) >= 0x0100) { 1000 /* IBM Broadway */ 1001 revfmt = REVFMT_HEX; 1002 } 1003 1004 if (cp->name[0] != '\0') { 1005 n = snprintf(str, len, "%s (rev ", cp->name); 1006 } else { 1007 n = snprintf(str, len, "Version %#x (Revision ", vers); 1008 } 1009 if (len > n) { 1010 switch (revfmt) { 1011 case REVFMT_MAJMIN: 1012 snprintf(str + n, len - n, "%u.%u)", major, minor); 1013 break; 1014 case REVFMT_HEX: 1015 snprintf(str + n, len - n, "0x%04x)", rev); 1016 break; 1017 case REVFMT_DEC: 1018 snprintf(str + n, len - n, "%u)", rev); 1019 break; 1020 } 1021 } 1022 } 1023 1024 #ifdef L2CR_CONFIG 1025 u_int l2cr_config = L2CR_CONFIG; 1026 #else 1027 u_int l2cr_config = 0; 1028 #endif 1029 1030 #ifdef L3CR_CONFIG 1031 u_int l3cr_config = L3CR_CONFIG; 1032 #else 1033 u_int l3cr_config = 0; 1034 #endif 1035 1036 void 1037 cpu_enable_l2cr(register_t l2cr) 1038 { 1039 register_t msr, x; 1040 uint16_t vers; 1041 1042 vers = mfpvr() >> 16; 1043 1044 if (vers == IBMESPRESSO && cpu_number() == 1) { 1045 /* Enable larger cache on core 1 */ 1046 l2cr |= L2SIZ_512K; 1047 } 1048 1049 /* Disable interrupts and set the cache config bits. */ 1050 msr = mfmsr(); 1051 mtmsr(msr & ~PSL_EE); 1052 #ifdef ALTIVEC 1053 if (cpu_altivec) 1054 __asm volatile("dssall"); 1055 #endif 1056 __asm volatile("sync"); 1057 mtspr(SPR_L2CR, l2cr & ~L2CR_L2E); 1058 __asm volatile("sync"); 1059 1060 /* Wait for L2 clock to be stable (640 L2 clocks). */ 1061 delay(100); 1062 1063 /* Invalidate all L2 contents. */ 1064 if (MPC745X_P(vers)) { 1065 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 1066 do { 1067 x = mfspr(SPR_L2CR); 1068 } while (x & L2CR_L2I); 1069 } else { 1070 mtspr(SPR_L2CR, l2cr | L2CR_L2I); 1071 do { 1072 x = mfspr(SPR_L2CR); 1073 } while (x & L2CR_L2IP); 1074 } 1075 /* Enable L2 cache. */ 1076 l2cr |= L2CR_L2E; 1077 mtspr(SPR_L2CR, l2cr); 1078 mtmsr(msr); 1079 } 1080 1081 void 1082 cpu_enable_l3cr(register_t l3cr) 1083 { 1084 register_t x; 1085 1086 /* By The Book (numbered steps from section 3.7.1.3 of MPC7450UM) */ 1087 1088 /* 1089 * 1: Set all L3CR bits for final config except L3E, L3I, L3PE, and 1090 * L3CLKEN. (also mask off reserved bits in case they were included 1091 * in L3CR_CONFIG) 1092 */ 1093 l3cr &= ~(L3CR_L3E|L3CR_L3I|L3CR_L3PE|L3CR_L3CLKEN|L3CR_RESERVED); 1094 mtspr(SPR_L3CR, l3cr); 1095 1096 /* 2: Set L3CR[5] (otherwise reserved bit) to 1 */ 1097 l3cr |= 0x04000000; 1098 mtspr(SPR_L3CR, l3cr); 1099 1100 /* 3: Set L3CLKEN to 1*/ 1101 l3cr |= L3CR_L3CLKEN; 1102 mtspr(SPR_L3CR, l3cr); 1103 1104 /* 4/5: Perform a global cache invalidate (ref section 3.7.3.6) */ 1105 __asm volatile("dssall;sync"); 1106 /* L3 cache is already disabled, no need to clear L3E */ 1107 mtspr(SPR_L3CR, l3cr|L3CR_L3I); 1108 do { 1109 x = mfspr(SPR_L3CR); 1110 } while (x & L3CR_L3I); 1111 1112 /* 6: Clear L3CLKEN to 0 */ 1113 l3cr &= ~L3CR_L3CLKEN; 1114 mtspr(SPR_L3CR, l3cr); 1115 1116 /* 7: Perform a 'sync' and wait at least 100 CPU cycles */ 1117 __asm volatile("sync"); 1118 delay(100); 1119 1120 /* 8: Set L3E and L3CLKEN */ 1121 l3cr |= (L3CR_L3E|L3CR_L3CLKEN); 1122 mtspr(SPR_L3CR, l3cr); 1123 1124 /* 9: Perform a 'sync' and wait at least 100 CPU cycles */ 1125 __asm volatile("sync"); 1126 delay(100); 1127 } 1128 1129 void 1130 cpu_config_l2cr(int pvr) 1131 { 1132 register_t l2cr; 1133 u_int vers = (pvr >> 16) & 0xffff; 1134 1135 l2cr = mfspr(SPR_L2CR); 1136 1137 /* 1138 * For MP systems, the firmware may only configure the L2 cache 1139 * on the first CPU. In this case, assume that the other CPUs 1140 * should use the same value for L2CR. 1141 */ 1142 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1143 l2cr_config = l2cr; 1144 } 1145 1146 /* 1147 * Configure L2 cache if not enabled. 1148 */ 1149 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1150 cpu_enable_l2cr(l2cr_config); 1151 l2cr = mfspr(SPR_L2CR); 1152 } 1153 1154 if ((l2cr & L2CR_L2E) == 0) { 1155 aprint_normal(" L2 cache present but not enabled "); 1156 return; 1157 } 1158 aprint_normal(","); 1159 1160 switch (vers) { 1161 case IBM750FX: 1162 case IBM750GX: 1163 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1164 break; 1165 case IBMESPRESSO: 1166 cpu_fmttab_print(cpu_espresso_l2cr_formats, l2cr); 1167 break; 1168 case MPC750: 1169 if ((pvr & 0xffffff00) == 0x00082200 /* IBM750CX */ || 1170 (pvr & 0xffffef00) == 0x00082300 /* IBM750CXe */) { 1171 cpu_fmttab_print(cpu_ibm750_l2cr_formats, l2cr); 1172 } else if ((pvr & 0xfffff0e0) == 0x00087000 /* IBM750CL */) { 1173 cpu_fmttab_print(cpu_ibm750cl_l2cr_formats, l2cr); 1174 } else { 1175 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1176 } 1177 break; 1178 case MPC7447A: 1179 case MPC7457: 1180 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1181 return; 1182 case MPC7448: 1183 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1184 return; 1185 case MPC7450: 1186 case MPC7455: 1187 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1188 break; 1189 default: 1190 cpu_fmttab_print(cpu_l2cr_formats, l2cr); 1191 break; 1192 } 1193 } 1194 1195 void 1196 cpu_config_l3cr(int vers) 1197 { 1198 register_t l2cr; 1199 register_t l3cr; 1200 1201 l2cr = mfspr(SPR_L2CR); 1202 1203 /* 1204 * For MP systems, the firmware may only configure the L2 cache 1205 * on the first CPU. In this case, assume that the other CPUs 1206 * should use the same value for L2CR. 1207 */ 1208 if ((l2cr & L2CR_L2E) != 0 && l2cr_config == 0) { 1209 l2cr_config = l2cr; 1210 } 1211 1212 /* 1213 * Configure L2 cache if not enabled. 1214 */ 1215 if ((l2cr & L2CR_L2E) == 0 && l2cr_config != 0) { 1216 cpu_enable_l2cr(l2cr_config); 1217 l2cr = mfspr(SPR_L2CR); 1218 } 1219 1220 aprint_normal(","); 1221 switch (vers) { 1222 case MPC7447A: 1223 case MPC7457: 1224 cpu_fmttab_print(cpu_7457_l2cr_formats, l2cr); 1225 return; 1226 case MPC7448: 1227 cpu_fmttab_print(cpu_7448_l2cr_formats, l2cr); 1228 return; 1229 default: 1230 cpu_fmttab_print(cpu_7450_l2cr_formats, l2cr); 1231 break; 1232 } 1233 1234 l3cr = mfspr(SPR_L3CR); 1235 1236 /* 1237 * For MP systems, the firmware may only configure the L3 cache 1238 * on the first CPU. In this case, assume that the other CPUs 1239 * should use the same value for L3CR. 1240 */ 1241 if ((l3cr & L3CR_L3E) != 0 && l3cr_config == 0) { 1242 l3cr_config = l3cr; 1243 } 1244 1245 /* 1246 * Configure L3 cache if not enabled. 1247 */ 1248 if ((l3cr & L3CR_L3E) == 0 && l3cr_config != 0) { 1249 cpu_enable_l3cr(l3cr_config); 1250 l3cr = mfspr(SPR_L3CR); 1251 } 1252 1253 if (l3cr & L3CR_L3E) { 1254 aprint_normal(","); 1255 cpu_fmttab_print(cpu_7450_l3cr_formats, l3cr); 1256 } 1257 } 1258 1259 void 1260 cpu_probe_speed(struct cpu_info *ci) 1261 { 1262 uint64_t cps; 1263 1264 mtspr(SPR_MMCR0, MMCR0_FC); 1265 mtspr(SPR_PMC1, 0); 1266 mtspr(SPR_MMCR0, MMCR0_PMC1SEL(PMCN_CYCLES)); 1267 delay(100000); 1268 cps = (mfspr(SPR_PMC1) * 10) + 4999; 1269 1270 mtspr(SPR_MMCR0, MMCR0_FC); 1271 1272 ci->ci_khz = (cps * cpu_get_dfs()) / 1000; 1273 } 1274 1275 /* 1276 * Read the Dynamic Frequency Switching state and return a divisor for 1277 * the maximum frequency. 1278 */ 1279 int 1280 cpu_get_dfs(void) 1281 { 1282 u_int pvr, vers; 1283 1284 pvr = mfpvr(); 1285 vers = pvr >> 16; 1286 1287 switch (vers) { 1288 case MPC7448: 1289 if (mfspr(SPR_HID1) & HID1_DFS4) 1290 return 4; 1291 /* FALLTHROUGH */ 1292 case MPC7447A: 1293 if (mfspr(SPR_HID1) & HID1_DFS2) 1294 return 2; 1295 } 1296 return 1; 1297 } 1298 1299 /* 1300 * Set the Dynamic Frequency Switching divisor the same for all cpus. 1301 */ 1302 void 1303 cpu_set_dfs(int div) 1304 { 1305 u_int dfs_mask, pvr, vers; 1306 1307 pvr = mfpvr(); 1308 vers = pvr >> 16; 1309 dfs_mask = 0; 1310 1311 switch (vers) { 1312 case MPC7448: 1313 dfs_mask |= HID1_DFS4; 1314 /* FALLTHROUGH */ 1315 case MPC7447A: 1316 dfs_mask |= HID1_DFS2; 1317 break; 1318 default: 1319 printf("cpu_set_dfs: DFS not supported\n"); 1320 return; 1321 1322 } 1323 #ifdef MULTIPROCESSOR 1324 uint64_t where; 1325 where = xc_broadcast(0, (xcfunc_t)cpu_set_dfs_xcall, &div, &dfs_mask); 1326 xc_wait(where); 1327 #else 1328 cpu_set_dfs_xcall(&div, &dfs_mask); 1329 #endif 1330 } 1331 1332 static void 1333 cpu_set_dfs_xcall(void *arg1, void *arg2) 1334 { 1335 u_int dfs_mask, hid1, old_hid1; 1336 int *divisor, s; 1337 1338 divisor = arg1; 1339 dfs_mask = *(u_int *)arg2; 1340 1341 s = splhigh(); 1342 hid1 = old_hid1 = mfspr(SPR_HID1); 1343 1344 switch (*divisor) { 1345 case 1: 1346 hid1 &= ~dfs_mask; 1347 break; 1348 case 2: 1349 hid1 &= ~(dfs_mask & HID1_DFS4); 1350 hid1 |= dfs_mask & HID1_DFS2; 1351 break; 1352 case 4: 1353 hid1 &= ~(dfs_mask & HID1_DFS2); 1354 hid1 |= dfs_mask & HID1_DFS4; 1355 break; 1356 } 1357 1358 if (hid1 != old_hid1) { 1359 __asm volatile("sync"); 1360 mtspr(SPR_HID1, hid1); 1361 __asm volatile("sync;isync"); 1362 } 1363 1364 splx(s); 1365 } 1366 1367 #if NSYSMON_ENVSYS > 0 1368 void 1369 cpu_tau_setup(struct cpu_info *ci) 1370 { 1371 struct sysmon_envsys *sme; 1372 int error, therm_delay; 1373 u_int pvr, vers; 1374 1375 pvr = mfpvr(); 1376 vers = pvr >> 16; 1377 1378 if (vers == MPC750 && (pvr & 0xf000) == 0x7000 && 1379 (pvr & 0x0f00) >= 0x0100) { 1380 /* Broadway has dummy TAU registers, just ignore it. */ 1381 return; 1382 } 1383 1384 mtspr(SPR_THRM1, SPR_THRM_VALID); 1385 mtspr(SPR_THRM2, 0); 1386 1387 /* 1388 * we need to figure out how much 20+us in units of CPU clock cycles 1389 * are 1390 */ 1391 1392 therm_delay = ci->ci_khz / 40; /* 25us just to be safe */ 1393 1394 mtspr(SPR_THRM3, SPR_THRM_TIMER(therm_delay) | SPR_THRM_ENABLE); 1395 1396 sme = sysmon_envsys_create(); 1397 1398 sensor.units = ENVSYS_STEMP; 1399 sensor.state = ENVSYS_SINVALID; 1400 (void)strlcpy(sensor.desc, "CPU Temp", sizeof(sensor.desc)); 1401 if (sysmon_envsys_sensor_attach(sme, &sensor)) { 1402 sysmon_envsys_destroy(sme); 1403 return; 1404 } 1405 1406 sme->sme_name = device_xname(ci->ci_dev); 1407 sme->sme_cookie = ci; 1408 sme->sme_refresh = cpu_tau_refresh; 1409 1410 if ((error = sysmon_envsys_register(sme)) != 0) { 1411 aprint_error_dev(ci->ci_dev, 1412 " unable to register with sysmon (%d)\n", error); 1413 sysmon_envsys_destroy(sme); 1414 } 1415 } 1416 1417 /* Find the temperature of the CPU. */ 1418 void 1419 cpu_tau_refresh(struct sysmon_envsys *sme, envsys_data_t *edata) 1420 { 1421 int i, threshold, count; 1422 1423 threshold = 64; /* Half of the 7-bit sensor range */ 1424 1425 /* Successive-approximation code adapted from Motorola 1426 * application note AN1800/D, "Programming the Thermal Assist 1427 * Unit in the MPC750 Microprocessor". 1428 */ 1429 for (i = 5; i >= 0 ; i--) { 1430 mtspr(SPR_THRM1, 1431 SPR_THRM_THRESHOLD(threshold) | SPR_THRM_VALID); 1432 count = 0; 1433 while ((count < 100000) && 1434 ((mfspr(SPR_THRM1) & SPR_THRM_TIV) == 0)) { 1435 count++; 1436 delay(1); 1437 } 1438 if (mfspr(SPR_THRM1) & SPR_THRM_TIN) { 1439 /* The interrupt bit was set, meaning the 1440 * temperature was above the threshold 1441 */ 1442 threshold += 1 << i; 1443 } else { 1444 /* Temperature was below the threshold */ 1445 threshold -= 1 << i; 1446 } 1447 } 1448 threshold += 2; 1449 1450 /* Convert the temperature in degrees C to microkelvin */ 1451 edata->value_cur = (threshold * 1000000) + 273150000; 1452 edata->state = ENVSYS_SVALID; 1453 } 1454 #endif /* NSYSMON_ENVSYS > 0 */ 1455 1456 #ifdef MULTIPROCESSOR 1457 volatile u_int cpu_spinstart_ack, cpu_spinstart_cpunum; 1458 1459 int 1460 cpu_spinup(device_t self, struct cpu_info *ci) 1461 { 1462 volatile struct cpu_hatch_data hatch_data, *h = &hatch_data; 1463 struct pglist mlist; 1464 int i, error; 1465 char *hp; 1466 1467 KASSERT(ci != curcpu()); 1468 1469 /* Now allocate a hatch stack */ 1470 error = uvm_pglistalloc(HATCH_STACK_SIZE, 0x10000, 0x10000000, 16, 0, 1471 &mlist, 1, 1); 1472 if (error) { 1473 aprint_error(": unable to allocate hatch stack\n"); 1474 return -1; 1475 } 1476 1477 hp = (void *)VM_PAGE_TO_PHYS(TAILQ_FIRST(&mlist)); 1478 memset(hp, 0, HATCH_STACK_SIZE); 1479 1480 /* Initialize secondary cpu's initial lwp to its idlelwp. */ 1481 ci->ci_curlwp = ci->ci_data.cpu_idlelwp; 1482 ci->ci_curpcb = lwp_getpcb(ci->ci_curlwp); 1483 ci->ci_curpm = ci->ci_curpcb->pcb_pm; 1484 ci->ci_battable = battable; 1485 1486 cpu_hatch_data = h; 1487 h->hatch_running = 0; 1488 h->hatch_self = self; 1489 h->hatch_ci = ci; 1490 h->hatch_pir = ci->ci_cpuid; 1491 1492 cpu_hatch_stack = (uint32_t)hp + HATCH_STACK_SIZE - CALLFRAMELEN; 1493 ci->ci_lasttb = cpu_info[0].ci_lasttb; 1494 1495 /* copy special registers */ 1496 1497 h->hatch_hid0 = mfspr(SPR_HID0); 1498 #if defined(PPC_OEA64_BRIDGE) || defined (_ARCH_PPC64) 1499 h->hatch_hid1 = mfspr(SPR_HID1); 1500 h->hatch_hid4 = mfspr(SPR_HID4); 1501 h->hatch_hid5 = mfspr(SPR_HID5); 1502 #endif 1503 1504 __asm volatile ("mfsdr1 %0" : "=r"(h->hatch_sdr1)); 1505 for (i = 0; i < 16; i++) { 1506 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1507 "r"(i << ADDR_SR_SHFT)); 1508 } 1509 if (oeacpufeat & OEACPU_64) 1510 h->hatch_asr = mfspr(SPR_ASR); 1511 else 1512 h->hatch_asr = 0; 1513 1514 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1515 /* copy the bat regs */ 1516 __asm volatile ("mfibatu %0,0" : "=r"(h->hatch_ibatu[0])); 1517 __asm volatile ("mfibatl %0,0" : "=r"(h->hatch_ibatl[0])); 1518 __asm volatile ("mfibatu %0,1" : "=r"(h->hatch_ibatu[1])); 1519 __asm volatile ("mfibatl %0,1" : "=r"(h->hatch_ibatl[1])); 1520 __asm volatile ("mfibatu %0,2" : "=r"(h->hatch_ibatu[2])); 1521 __asm volatile ("mfibatl %0,2" : "=r"(h->hatch_ibatl[2])); 1522 __asm volatile ("mfibatu %0,3" : "=r"(h->hatch_ibatu[3])); 1523 __asm volatile ("mfibatl %0,3" : "=r"(h->hatch_ibatl[3])); 1524 __asm volatile ("mfdbatu %0,0" : "=r"(h->hatch_dbatu[0])); 1525 __asm volatile ("mfdbatl %0,0" : "=r"(h->hatch_dbatl[0])); 1526 __asm volatile ("mfdbatu %0,1" : "=r"(h->hatch_dbatu[1])); 1527 __asm volatile ("mfdbatl %0,1" : "=r"(h->hatch_dbatl[1])); 1528 __asm volatile ("mfdbatu %0,2" : "=r"(h->hatch_dbatu[2])); 1529 __asm volatile ("mfdbatl %0,2" : "=r"(h->hatch_dbatl[2])); 1530 __asm volatile ("mfdbatu %0,3" : "=r"(h->hatch_dbatu[3])); 1531 __asm volatile ("mfdbatl %0,3" : "=r"(h->hatch_dbatl[3])); 1532 __asm volatile ("sync; isync"); 1533 } 1534 1535 if (md_setup_trampoline(h, ci) == -1) 1536 return -1; 1537 md_presync_timebase(h); 1538 md_start_timebase(h); 1539 1540 /* wait for secondary printf */ 1541 1542 delay(200000); 1543 1544 #ifdef CACHE_PROTO_MEI 1545 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1546 __asm volatile ("sync; isync"); 1547 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1548 __asm volatile ("sync; isync"); 1549 #endif 1550 int hatch_bail = 0; 1551 while ((h->hatch_running < 1) && (hatch_bail < 100000)) { 1552 delay(1); 1553 hatch_bail++; 1554 #ifdef CACHE_PROTO_MEI 1555 __asm volatile ("dcbi 0,%0"::"r"(&h->hatch_running):"memory"); 1556 __asm volatile ("sync; isync"); 1557 __asm volatile ("dcbst 0,%0"::"r"(&h->hatch_running):"memory"); 1558 __asm volatile ("sync; isync"); 1559 #endif 1560 } 1561 if (h->hatch_running < 1) { 1562 #ifdef CACHE_PROTO_MEI 1563 __asm volatile ("dcbi 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1564 __asm volatile ("sync; isync"); 1565 __asm volatile ("dcbst 0,%0"::"r"(&cpu_spinstart_ack):"memory"); 1566 __asm volatile ("sync; isync"); 1567 #endif 1568 aprint_error("%d:CPU %d didn't start %d\n", cpu_spinstart_ack, 1569 ci->ci_cpuid, cpu_spinstart_ack); 1570 console_debugger(); 1571 return -1; 1572 } 1573 1574 return 0; 1575 } 1576 1577 static volatile int start_secondary_cpu; 1578 1579 register_t 1580 cpu_hatch(void) 1581 { 1582 volatile struct cpu_hatch_data *h = cpu_hatch_data; 1583 volatile struct cpuset_info * const csi = &cpuset_info; 1584 struct cpu_info * const ci = h->hatch_ci; 1585 struct pcb *pcb; 1586 u_int msr; 1587 int i; 1588 1589 /* Initialize timebase. */ 1590 __asm ("mttbl %0; mttbu %0; mttbl %0" :: "r"(0)); 1591 1592 /* 1593 * Set PIR (Processor Identification Register). i.e. whoami 1594 * Note that PIR is read-only on some CPU versions, so we write to it 1595 * only if it has a different value than we need. 1596 */ 1597 1598 msr = mfspr(SPR_PIR); 1599 if (msr != h->hatch_pir) 1600 mtspr(SPR_PIR, h->hatch_pir); 1601 1602 __asm volatile ("mtsprg0 %0" :: "r"(ci)); 1603 curlwp = ci->ci_curlwp; 1604 cpu_spinstart_ack = 0; 1605 1606 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1607 /* Initialize MMU. */ 1608 __asm ("mtibatu 0,%0" :: "r"(h->hatch_ibatu[0])); 1609 __asm ("mtibatl 0,%0" :: "r"(h->hatch_ibatl[0])); 1610 __asm ("mtibatu 1,%0" :: "r"(h->hatch_ibatu[1])); 1611 __asm ("mtibatl 1,%0" :: "r"(h->hatch_ibatl[1])); 1612 __asm ("mtibatu 2,%0" :: "r"(h->hatch_ibatu[2])); 1613 __asm ("mtibatl 2,%0" :: "r"(h->hatch_ibatl[2])); 1614 __asm ("mtibatu 3,%0" :: "r"(h->hatch_ibatu[3])); 1615 __asm ("mtibatl 3,%0" :: "r"(h->hatch_ibatl[3])); 1616 __asm ("mtdbatu 0,%0" :: "r"(h->hatch_dbatu[0])); 1617 __asm ("mtdbatl 0,%0" :: "r"(h->hatch_dbatl[0])); 1618 __asm ("mtdbatu 1,%0" :: "r"(h->hatch_dbatu[1])); 1619 __asm ("mtdbatl 1,%0" :: "r"(h->hatch_dbatl[1])); 1620 __asm ("mtdbatu 2,%0" :: "r"(h->hatch_dbatu[2])); 1621 __asm ("mtdbatl 2,%0" :: "r"(h->hatch_dbatl[2])); 1622 __asm ("mtdbatu 3,%0" :: "r"(h->hatch_dbatu[3])); 1623 __asm ("mtdbatl 3,%0" :: "r"(h->hatch_dbatl[3])); 1624 } 1625 1626 #ifdef PPC_OEA64_BRIDGE 1627 if ((oeacpufeat & OEACPU_64_BRIDGE) != 0) { 1628 1629 mtspr64(SPR_HID0, h->hatch_hid0); 1630 mtspr64(SPR_HID1, h->hatch_hid1); 1631 mtspr64(SPR_HID4, h->hatch_hid4); 1632 mtspr64(SPR_HID5, h->hatch_hid5); 1633 mtspr64(SPR_HIOR, 0); 1634 } else 1635 #endif 1636 mtspr(SPR_HID0, h->hatch_hid0); 1637 1638 if ((oeacpufeat & OEACPU_NOBAT) == 0) { 1639 __asm ("mtibatl 0,%0; mtibatu 0,%1; mtdbatl 0,%0; mtdbatu 0,%1;" 1640 :: "r"(battable[0].batl), "r"(battable[0].batu)); 1641 } 1642 1643 __asm volatile ("sync"); 1644 for (i = 0; i < 16; i++) 1645 __asm ("mtsrin %0,%1" :: "r"(h->hatch_sr[i]), "r"(i << ADDR_SR_SHFT)); 1646 __asm volatile ("sync; isync"); 1647 1648 if (oeacpufeat & OEACPU_64) 1649 mtspr(SPR_ASR, h->hatch_asr); 1650 1651 cpu_spinstart_ack = 1; 1652 __asm ("ptesync"); 1653 __asm ("mtsdr1 %0" :: "r"(h->hatch_sdr1)); 1654 __asm volatile ("sync; isync"); 1655 1656 cpu_spinstart_ack = 5; 1657 for (i = 0; i < 16; i++) 1658 __asm ("mfsrin %0,%1" : "=r"(h->hatch_sr[i]) : 1659 "r"(i << ADDR_SR_SHFT)); 1660 1661 /* Enable I/D address translations. */ 1662 msr = mfmsr(); 1663 msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI; 1664 mtmsr(msr); 1665 __asm volatile ("sync; isync"); 1666 cpu_spinstart_ack = 2; 1667 1668 md_sync_timebase(h); 1669 1670 cpu_setup(h->hatch_self, ci); 1671 1672 kcpuset_atomic_set(csi->cpus_hatched, cpu_number()); 1673 1674 h->hatch_running = 1; 1675 __asm volatile ("sync; isync"); 1676 1677 while (start_secondary_cpu == 0) 1678 ; 1679 1680 __asm volatile ("sync; isync"); 1681 1682 aprint_normal("cpu%d started\n", cpu_number()); 1683 __asm volatile ("mtdec %0" :: "r"(ticks_per_intr)); 1684 1685 md_setup_interrupts(); 1686 1687 ci->ci_ipending = 0; 1688 ci->ci_cpl = 0; 1689 1690 kcpuset_atomic_set(csi->cpus_running, cpu_number()); 1691 1692 mtmsr(mfmsr() | PSL_EE); 1693 pcb = lwp_getpcb(ci->ci_data.cpu_idlelwp); 1694 return pcb->pcb_sp; 1695 } 1696 1697 void 1698 cpu_boot_secondary_processors(void) 1699 { 1700 start_secondary_cpu = 1; 1701 __asm volatile ("sync"); 1702 } 1703 1704 #endif /*MULTIPROCESSOR*/ 1705
Indexes created Mon Feb 23 16:20:21 UTC 2026