| History log of /src/sys/arch/powerpc/oea/cpu_subr.c |
| Revision | | Date | Author | Comments |
| 1.111 |
| 17-Feb-2025 |
jmcneill | powerpc: Identify Broadway CPU.
Use hex to report Broadway revision and ignore TAU as it does not exist
on this processor.
|
| 1.110 |
| 08-Sep-2024 |
andvar | Use console_debbuger() or DDB guards for Debugger() and db_stack_trace_print().
Should allow to build these files without DDB enabled option.
|
| 1.109 |
| 20-Jan-2024 |
jmcneill | powerpc: oea: Decode IBM750CL L2 cache information.
|
| 1.108 |
| 21-Mar-2021 |
rin | branches: 1.108.16;
Fix copy-paste.
|
| 1.107 |
| 26-Feb-2021 |
thorpej | branches: 1.107.2;
Split cpu_model_init() into cpu_features_probe() and cpu_features_enable()
so that early bootstrap can do those two steps independently, if needed.
Continue to provide a cpu_model_init() wrapper for now.
|
| 1.106 |
| 26-Feb-2021 |
thorpej | Declare oeacpufeat once, in powerpc/oea/cpu_subr.c, rather than in
N different locore.S files.
|
| 1.105 |
| 24-Feb-2021 |
thorpej | Add a provision for a per-cpu battable. Each CPU starts with the global
one, but this allows CPUs to temporarily switch to an alternate battable
if needed.
|
| 1.104 |
| 06-Jul-2020 |
rin | branches: 1.104.2;
Include missing opt_ppcarch.h.
|
| 1.103 |
| 06-Jul-2020 |
rin | Style and cosmetic changes. No binary changes intended.
|
| 1.102 |
| 25-Oct-2019 |
macallan | register the IPI before spinning up CPUs, and make sure to do it exactly once
with this, and previous commits, G5s with four CPUs work
tested by Romain Dolbeau
|
| 1.101 |
| 20-Sep-2019 |
macallan | don't enable NAP mode on 7450 CPUs - my Quicksilver has two of those and we
hang hard shortly after boot with NAP enabled, even on UP kernels
|
| 1.100 |
| 02-Aug-2019 |
macallan | first step to address PR54331:
poll h->hatch_running for a bit instead of blindly relying on a fixed timeout
for secondary CPUs to wake up and get ready
needs more testing, possibly pullup
|
| 1.99 |
| 06-Feb-2019 |
mrg | - add or adjust fallthru comments
|
| 1.98 |
| 06-Jan-2019 |
phx | Only execute dssall when the CPU has the Altivec instruction set extension.
|
| 1.97 |
| 15-Jun-2018 |
uwe | branches: 1.97.2;
Fix fmttab value for L2CR_L2PE (parity enabled) so that we don't print
self-contradictory "no parity parity enabled".
|
| 1.96 |
| 08-Jun-2018 |
macallan | when switching CPU speed using DFS, only use xcalls on MULTIPROCESSOR kernels
|
| 1.95 |
| 01-Jun-2018 |
macallan | add clock speed control for 970MP CPUs
|
| 1.94 |
| 25-May-2018 |
macallan | copy HID1 from the boot CPU to secondary CPUs as well on 64bit CPUs
now the 2nd CPU on my G5s runs at full speed
|
| 1.93 |
| 04-May-2018 |
macallan | save & restore HID4 and HID5, zero SPR_HIOR on 970
|
| 1.92 |
| 29-Mar-2018 |
macallan | fix build for 32bit non-bridge SMP kernels
|
| 1.91 |
| 22-Mar-2018 |
macallan | first step towards G5 SMP:
- only save/restore BATs on CPUs that have them
- treat HID0 as 64bit on 64bit CPUs
|
| 1.90 |
| 04-Mar-2018 |
mrg | branches: 1.90.2;
avoid 32 bit only code in 64 bit mode.
|
| 1.89 |
| 16-Feb-2018 |
macallan | use mtspr64() in bridge mode
|
| 1.88 |
| 21-Jan-2018 |
mrg | fix ofppc/pegasosII (and maybe others).
don't assume PPC_OEA64_BRIDGE means we have a 64 bit cpu (code
for 64 bit in bridge and normal 32 bit can co-exist due to
fixups the early boot code does has, and ofppc builds GENERIC
this way):
- fix mtmsr()/mfmsr() to use the right method based upon the
actually cpu booted on.
- fix cpu_setup() to have 32 bit and 64 bit hid0 variables
and operate on the right one based upon the current cpu.
restore a minor optimisation of not writing hid0 if it
didn't change.
in set_timebase() check if OF_finddevice("/cpus/@0") failed
and returned -1 before using it for OF_getprop().
|
| 1.87 |
| 06-Jan-2018 |
snj | fix a few typos in comments
|
| 1.86 |
| 30-Sep-2017 |
macallan | use 7450 HID0 bitmask on 7447A and 7448 as well
|
| 1.85 |
| 11-Jul-2017 |
maya | inline HAVE_64BIT_HID0 and remove macro definition.
Fixes llvm INSTALL kernel build, which failed with:
error: macro expansion producing 'defined' has undefined behavior
|
| 1.84 |
| 07-Jul-2017 |
macallan | remove accidential debug printf()
|
| 1.83 |
| 07-Jul-2017 |
macallan | deal with ppc970's HID0
|
| 1.82 |
| 24-Mar-2014 |
christos | branches: 1.82.6;
use cpu_{g,s}etmodel
|
| 1.81 |
| 14-Mar-2014 |
mrg | remove various set-but-unused variables.
|
| 1.80 |
| 03-Nov-2013 |
mrg | - remove set but unused variables
- move some variables inside their relevant use #ifdef
|
| 1.79 |
| 22-Sep-2013 |
matt | Fix c&p bug.
|
| 1.78 |
| 22-Sep-2013 |
matt | Disable XBSEN for the 7450.
|
| 1.77 |
| 22-Sep-2013 |
matt | Make sure ABE/SYNCBE are enabled in HID1 for the 7450 CPUs
Enable XBSEN for the 7450.
|
| 1.76 |
| 20-Oct-2012 |
kiyohara | branches: 1.76.2;
Support Cache Protocol 'MEI' with MULTIPROCESSOR.
|
| 1.75 |
| 20-Oct-2012 |
kiyohara | Fix broken cpu_hatch_stack.
And define macro HATCH_STACK_SIZE.
|
| 1.74 |
| 20-Oct-2012 |
kiyohara | Remove white-spaces. And remove unused 'extern void tlbia()'.
|
| 1.73 |
| 01-Feb-2012 |
matt | branches: 1.73.6;
Use kmem instead of malloc. Remove unneeded <sys/malloc.h> includes.
|
| 1.72 |
| 01-Feb-2012 |
matt | Enable XBSEN and HIGHBAT for OEA 7455 and related CPUs.
The BAT entries now have a resolution of 8MB. (Adjacent entries are merged
up to a total of 2GB per entry).
|
| 1.71 |
| 23-Jan-2012 |
phx | Insert some missing aprint_naive().
|
| 1.70 |
| 29-Jun-2011 |
matt | branches: 1.70.2; 1.70.6;
Cleanup hatch names.
Add cpuset_info.
|
| 1.69 |
| 21-Jun-2011 |
matt | Reap the ci_ev_soft* evcnts since every variant implements __HAVE_FAST_SOFTINTS
|
| 1.68 |
| 20-Jun-2011 |
pgoyette | Initialize sensor state before registering.
|
| 1.67 |
| 20-Jun-2011 |
matt | <arch/powerpc/... -> <powerpc/...
|
| 1.66 |
| 17-Jun-2011 |
matt | struct device * -> device_t
struct cfdata * -> cfdata_t
split device/softc (CFATTACH_DECL_NEW)
use device_accessors and device_private
constify
|
| 1.65 |
| 16-Jun-2011 |
matt | Make sure to set curlwp (aka r13) in cpu_hatch
|
| 1.64 |
| 12-Jun-2011 |
matt | Use mtsprg0 instead of mtsprg 0,r
|
| 1.63 |
| 05-Jun-2011 |
matt | Remove <machine/atomic.h>; use <sys/atomic.h> instead.
Add <powerpc/cpuset.h> (for mpc85xx pmap).
Add some initial MP code for mpc85xx
Rework ipi code to be common across all ppcs
Change PPC to keep curlwp in %r13 while in the kernel.
Move astpending from cpu_info to mdlwp
Improve cpu_need_resched to be more MP friendly.
|
| 1.62 |
| 12-Feb-2011 |
matt | branches: 1.62.2;
Add support for the IBM750GX (from Bob Lee).
|
| 1.61 |
| 18-Jan-2011 |
matt | branches: 1.61.2;
Fix some fallout from building the macppc GENERIC.MP.
|
| 1.60 |
| 18-Jan-2011 |
matt | Add support for BookE Freescale MPC85xx (e500 core) processors.
Add fast softint support for PowerPC (though only booke uses it).
Redo FPU/VEC support and add e500 SPE support.
Rework trap/intrs to use a common trapframe format.
Support SOFTFLOAT (no hardfloat or fpu emulation) for BookE.
|
| 1.59 |
| 06-Nov-2010 |
uebayasi | branches: 1.59.2;
Machine dependent code is considered as part of UVM. Include
internal API header.
|
| 1.58 |
| 05-Nov-2010 |
phx | Only read from HID1 when a G3 CPU was detected in cpu_get_dfs(), otherwise
the access might cause a PGM trap.
|
| 1.57 |
| 28-Oct-2010 |
macallan | Use nap mode on 750-ish CPUs
|
| 1.56 |
| 20-Oct-2010 |
phx | Support sysctl machdep.cpu_speed for 7447A and 7448 based Macs. On those
machines the CPU's DFS (Dynamic Frequency Switching) feature is used instead
of a GPIO to control the speed.
Two new functions in powerpc/oea/cpu_subr.c were introduced to support
reading and writing of DFS: cpu_get_dfs() and cpu_set_dfs(). Also works
for multiple CPUs, but not before interrupts are enabled.
|
| 1.55 |
| 25-Feb-2010 |
matt | branches: 1.55.2;
Adapt to spr.h breakup.
|
| 1.54 |
| 21-Nov-2009 |
rmind | branches: 1.54.2;
Use lwp_getpcb() on mips, powerpc and sh3, clean from struct user usage.
|
| 1.53 |
| 18-Mar-2009 |
cegger | Ansify function definitions w/o arguments. Generated with sed.
|
| 1.52 |
| 14-Mar-2009 |
dsl | Change about 4500 of the K&R function definitions to ANSI ones.
There are still about 1600 left, but they have ',' or /* ... */
in the actual variable definitions - which my awk script doesn't handle.
There are also many that need () -> (void).
(The script does handle misordered arguments.)
|
| 1.51 |
| 16-Dec-2008 |
christos | branches: 1.51.2;
replace bitmask_snprintf(9) with snprintb(3)
|
| 1.50 |
| 14-Oct-2008 |
macallan | branches: 1.50.2; 1.50.14;
Some fixes to the TAU support code:
- set the ADC time according to clock speed, not some magic number
- move some mtspr()s which we really only need to do once
- make our envsys_data_t static, this should fix PR 39411
|
| 1.49 |
| 04-Oct-2008 |
chs | in cpu_hatch(), set PIR when the current value is not what we need
rather than only when it's zero.
|
| 1.48 |
| 23-Sep-2008 |
macallan | properly 'probe' the MPC7400's L1 caches - before we'd fall through to
setting both to PAGE_SIZE
|
| 1.47 |
| 25-May-2008 |
chs | branches: 1.47.4;
add IBM970MP (used in the last model of powermac G5).
|
| 1.46 |
| 08-Apr-2008 |
garbled | branches: 1.46.2; 1.46.4; 1.46.6;
SMP support for ofppc. (finally) Much thanks to Matt Thomas for help in
figuring out all the crazy nuances of getting this working, and to
Michael Lorenz for testing/fixing my changes on macppc. Tested with a
quad-proc 7044-270.
Summary of changes:
Bumped CPU_MAXNUM to 16 on ofppc.
Added md_* routines to ofppc/cpu.c, to sync the timebase, and awaken the CPUs.
Fixed a bug in the test for a 64bit bridge cpu early in locore.S
Added code to set the interrupt priority for all CPUs with an openpic.
Change rtas to probe before cpus, to allow use of the rtas freeze/thaw
timebase code routines.
Fix CPU_INFO_FOREACH macro to iterate through detected cpus, not CPU_MAXNUM.
Change most uses of ci_cpuid to ci_index, to deal with CPUs that do not allow
writing to SPR_PIR. Don't write SPR_PIR unless the secondary cpu identifies
itself as 0.
Change the hatchstack/interrupt stack allocations to allocate a 8192byte
interrupt stack, and a 4096 byte hatch stack, align them to 16 bytes, and
allocate them no lower than 0x10000. Allocate them separately to prevent the
hatch stack corrupting the interrupt stack later on.
If the CPU is a 64bit cpu, copy SPR_ASR in cpu_hatch()
Set the idle stack to ci->ci_data.cpu_idlelwp->l_addr->u_pcb.pcb_sp.
Add OF_start_cpu(). Add a routine to ofwoea_initppc to spin up secondary
procs early, and place them into a spinloop waiting for the hatch routines
to be ready.
Modify the ipi routines to deal with openpics that reverse byte order on read
from an ipi register. (such as on the 7044)
Change the rtas setup to allocate the rtas physical base address above
the kernel, to avoid mucking up the hatch/interrupt stacks.
|
| 1.45 |
| 23-Feb-2008 |
matt | Detect HIGHBAT/XBSEN/HIGHSPRG to MPC74[45]x where x > 1
Enable above as appropriate.
|
| 1.44 |
| 14-Feb-2008 |
garbled | branches: 1.44.2; 1.44.6;
Some powerpc cleanup. Remove unneeded/bad usage of extern oeacpufeat.
Convert asm code to use %r register format. Done by comparison to
disassembled output, double checked with diff of dissasembled output
before and after, and test booted on my 7044.
|
| 1.43 |
| 05-Feb-2008 |
garbled | Replace as much of the hardcoded CACHELINESIZE with
curcpu()->ci_ci.dcache_line_size as I can. With this change, an ofppc kernel
compiled with both PPC_OEA and PPC_OEA64_BRIDGE defined, boots.
|
| 1.42 |
| 05-Feb-2008 |
garbled | Rewrite a big chunk of the pmap and locore code for powerpc to better
deal with the 64bit bridge mode. pmap changes by Matt Thomas, rest by myself.
Change pmap.c to work similar to exec_elf.c to allow us to compile in
multiple pmaps to a single kernel. This allows the pmap for bridge64 to
co-exist with the 32bit pmap.
Yank __HAVE_PMAP_PHYSSEG from all the oea code.
Add a new global, "oeacpufeat", which is used early in locore to determine
certain cpu features. This allows us to conditionalize code early in the boot
for certain CPUs that have special needs.
Yank most of the ifdef PPC_OEA_BRIDGE64 code from almost every file it was
found in. Some of it seemed incorrect, and my 7044 booted just fine
without it. It would appear that the bridge cpus treat BAT instructions
as nops, so they seem to be safe.
In ofppc, check the oeacpufeat, and if we are on a 64bit proc, clear
MSR[SF], and ASR[V].
With all of these changes, a kernel with both PPC_OEA and PPC_OEA_BRIDGE64
will boot on the POWERIII-2 cpu. However, it will not yet boot on a 32bit
cpu, because of CACHELINESIZE. Work remains to be done there to fix that.
|
| 1.41 |
| 17-Jan-2008 |
garbled | Add support to ofppc for the IBM 7044-270 machine. This is a POWER3-II
based machine. Currently the kernel to run on this machine is
incompatible with the standard GENERIC kernel, so for now, we have a
separate GENERIC_B64. Eventually, I hope to combine the two.
Please note, this is a port of 32bit ofppc, not a powerpc64 port.
Thanks to Matt Thomas and Kevin Bowling for helping to make this port
possible.
Summary of changes:
Change ofwpci to use the ofmethod config for configuring the PCI bus,
rather than indirect configuration.
Move the wiring of the interrupt controllers from at the start of the
boot, into the configuration of the first PCI bus.
Rewrite the map_isa_ioregs() hack to work on a machine without BATs
Fix a ton of bugs in the genofw_find_pics routine, and in the map_space code.
Split the pic_openpic into openpic_common and pic_openpic.
Create a new pic_distopenpic driver, for the distributed openpic found on
some newer IBM machines.
Fix a bad panic in pmap_extract on 64bit bridge mode
|
| 1.40 |
| 31-Dec-2007 |
garbled | On the 745x cpu, you have to invalidate cache slightly differently than
you do on the other cpus. Add an if statement that takes this into account.
|
| 1.39 |
| 31-Dec-2007 |
macallan | 'never try to fix more than one thing at once, especially if one is a crash'
backout bogus G4 CPU revision 'fix'
|
| 1.38 |
| 30-Dec-2007 |
macallan | Remove a superfluous /* FALLTHROUGH */
Also switch back to waiting for L2CR_L2IP in cpu_enable_l2cr() - now my 2nd
G4 spins up again.
|
| 1.37 |
| 30-Dec-2007 |
macallan | Fix a logic botch when setting up L3 cache - don't attempt to do so on CPUs
that can't have L3 cache. While there also fix revision reporting for MPC7400
so what we report matches MacOS X.
|
| 1.36 |
| 27-Dec-2007 |
garbled | Lots and lots of fixes to the cpu identification code, and dealing with
L2 and L3 cache initialization. Mostly to get the L2 enabled on the
pegasos, but since I had the manual, I fixed a few other things I saw
while I was there.
|
| 1.35 |
| 17-Nov-2007 |
kefren | branches: 1.35.6;
Initialize sensor's state
on behalf of xtraeme
|
| 1.34 |
| 16-Nov-2007 |
xtraeme | Extend the envsys2 API (one more time, sorry) as defined in:
http://mail-index.netbsd.org/tech-kern/2007/11/09/0001.html
sysmon_envsys_create() and sysmon_envsys_destroy() were added to
create/destroy sysmon_envsys objects (and its TAILQ/LIST for sensors/events).
sysmon_envsys_sensor_attach() and sysmon_envsys_sensor_detach() were
added to attach/detach sensors to a specified sysmon_envsys device.
The events framework is now per device and configurable via the
ENVSYS_SETDICTIONARY ioctl or /etc/envsys.conf and envstat(8).
Update all users and documentation to reflect these changes.
|
| 1.33 |
| 17-Oct-2007 |
garbled | branches: 1.33.2;
Merge the ppcoea-renovation branch to HEAD.
This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.
TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.
NOTES:
pmppc was removed as an arch, and moved to a evbppc target.
|
| 1.32 |
| 01-Jul-2007 |
xtraeme | branches: 1.32.8; 1.32.10; 1.32.12; 1.32.14;
Imported envsys 2, a brief description of the new features:
(Part 2: drivers)
* Support for detachable sensors.
* Cleaned up the API for simplicity and efficiency.
* Ability to send capacity/critical/warning events to powerd(8).
* Adapted all the code to the new locking order.
* Compatibility with the old envsys API: the ENVSYS_GTREINFO
and ENVSYS_GTREDATA ioctl(2)s are supported.
* Added support for a 'dictionary based communication channel' between
sysmon_power(9) and powerd(8), that means there is no 32 bytes event
size restriction anymore.
* Binary compatibility with old envstat(8) and powerd(8) via COMPAT_40.
* All drivers with the n^2 gtredata bug were fixed, PR kern/36226.
Tested by:
blymn: smsc(4).
bouyer: ipmi(4), mfi(4).
kefren: ug(4).
njoly: viaenv(4), adt7463.c.
riz: owtemp(4).
xtraeme: acpiacad(4), acpibat(4), acpitz(4), aiboost(4), it(4), lm(4).
|
| 1.31 |
| 25-Jun-2007 |
aymeric | Recognize the Freescale G2 cores: initialize cache line size, and doze mode
While there, fix the way the major version of a PowerPC processor is computed
|
| 1.30 |
| 02-Jun-2007 |
nisimura | - add MPC8245 to cpuname table.
|
| 1.29 |
| 17-May-2007 |
yamt | merge yamt-idlelwp branch. asked by core@. some ports still needs work.
from doc/BRANCHES:
idle lwp, and some changes depending on it.
1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.
|
| 1.28 |
| 30-Oct-2006 |
garbled | branches: 1.28.4; 1.28.8; 1.28.10; 1.28.16;
Make these files compile with -Wextra -Wno-unused.
|
| 1.27 |
| 05-Aug-2006 |
sanjayl | branches: 1.27.4; 1.27.6;
1st cut of Powermac G5 support (uses bridge mode).
|
| 1.26 |
| 24-Dec-2005 |
perry | branches: 1.26.4; 1.26.8;
Remove leading __ from __(const|inline|signed|volatile) -- it is obsolete.
|
| 1.25 |
| 11-Dec-2005 |
christos | merge ktrace-lwp.
|
| 1.24 |
| 02-Jun-2005 |
he | branches: 1.24.2;
Fix shadowing and cast qualification warnings.
|
| 1.23 |
| 03-Feb-2005 |
briggs | Keep track of the CPU's current speed (in kHz) in the cpu info structure,
if we can get it. May want to expand this in the future to include min
and max speeds for systems where we can adjust the speed.
|
| 1.22 |
| 21-Jan-2005 |
matt | branches: 1.22.2;
Add more support for MPC7447A/MPC7448.
|
| 1.21 |
| 20-Jan-2005 |
matt | Add entry for MPC7447A
|
| 1.20 |
| 19-Jan-2005 |
matt | Split the hw-dependent powermanglement into its own function and make
Idle call that. Add a ci_idlespin function pointer to cpu_info.
Update INIT_CPUINFO to initialize it to a naked 'blr' instruction.
In oea/cpu_subr.c, add cpu_idlespin and make ci_idlespin point to it.
|
| 1.19 |
| 11-Jan-2005 |
chs | branches: 1.19.2;
enable powersave mode on 7450 and family.
also, the HID0_DOZE bit in this context doesn't mean "doze",
it's actually "enable extra BATs". add an alias for this bit
and use it as appropriate.
|
| 1.18 |
| 07-Jan-2005 |
briggs | Allow MSR[POW] off for power saving on 604-era CPUs. From Tim Kelly.
XXX -- needs benchmarking
|
| 1.17 |
| 07-Jan-2005 |
briggs | Don't attempt to probe the cache with l2cr on 604ev. From Tim Kelly.
|
| 1.16 |
| 08-Dec-2004 |
briggs | Add MPC7400 to the list of CPUs for which we try to measure the speed.
Noticed missing by Tim Kelly.
|
| 1.15 |
| 06-Dec-2004 |
briggs | Minor (old) patch from me to correct CPU ID of 604e vs. 604ev.
Tested by Tim Kelly.
Also patched from Tim to
- Delay longer for second CPU spinup.
- Only attempt to print CPU speed and cache configuration on certain
CPU types.
|
| 1.14 |
| 26-Jun-2004 |
kleink | On OEA, turn PSL_USER* into runtime values appropriate for the CPU model
we're executing on; besides dealing with the bits not implemented in the
601's MSR it also removes the silent failure behaviour when passing
PSL_VEC set on a CPU not implementing it.
Also, fix those masks for the 4xx again.
|
| 1.13 |
| 11-Mar-2004 |
christos | PR/24741: Aymeric Vincent: Variable sme_flags isn't initialized to zero
|
| 1.12 |
| 17-Feb-2004 |
matt | Don't waste space on likely unused sysmon structure.
Instead malloc them as needed.
|
| 1.11 |
| 09-Oct-2003 |
matt | Add support for MPC74[45]7
|
| 1.10 |
| 04-Aug-2003 |
matt | Make that OEA based kernels can properly deal with kernel ISI faults. Now
that LKMs are supported, it is possible for a LKM page to be "outspilled"
resulting in a possible ISI fault. Try to spill the page back in.
|
| 1.9 |
| 15-Jul-2003 |
lukem | __KERNEL_RCSID()
|
| 1.8 |
| 10-Apr-2003 |
scw | branches: 1.8.2;
Re-read L2CR after enabling the L2 cache to avoid returning without
printing the cache details.
|
| 1.7 |
| 04-Apr-2003 |
matt | Rework l2cr/l3cr enabling/printing code. Make printing table driven.
|
| 1.6 |
| 02-Apr-2003 |
thorpej | Use PAGE_SIZE rather than NBPG.
|
| 1.5 |
| 29-Mar-2003 |
matt | Make sure to turn on the speed knobs in HID0 on the 745x.
|
| 1.4 |
| 15-Mar-2003 |
matt | s;backside;; and report L2CR_L2DO & L2CR_L2IO
|
| 1.3 |
| 14-Mar-2003 |
matt | Use aprint_normal. Print 2MB L2 sizes with 7410.
|
| 1.2 |
| 26-Feb-2003 |
jklos | Added L3CR_CONFIG for support of 745x G4 L3 cache configuration.
|
| 1.1 |
| 03-Feb-2003 |
matt | Rename PPC_MPC6XX to PPC_OEA (and any mpc6xx reference to oea).
|
| 1.8.2.8 |
| 10-Nov-2005 |
skrll | Sync with HEAD. Here we go again...
|
| 1.8.2.7 |
| 04-Feb-2005 |
skrll | Sync with HEAD.
|
| 1.8.2.6 |
| 24-Jan-2005 |
skrll | Sync with HEAD.
|
| 1.8.2.5 |
| 17-Jan-2005 |
skrll | Sync with HEAD.
|
| 1.8.2.4 |
| 18-Dec-2004 |
skrll | Sync with HEAD.
|
| 1.8.2.3 |
| 21-Sep-2004 |
skrll | Fix the sync with head I botched.
|
| 1.8.2.2 |
| 18-Sep-2004 |
skrll | Sync with HEAD.
|
| 1.8.2.1 |
| 03-Aug-2004 |
skrll | Sync with HEAD
|
| 1.19.2.1 |
| 29-Apr-2005 |
kent | sync with -current
|
| 1.22.2.1 |
| 12-Feb-2005 |
yamt | sync with head.
|
| 1.24.2.8 |
| 27-Feb-2008 |
yamt | sync with head.
|
| 1.24.2.7 |
| 11-Feb-2008 |
yamt | sync with head.
|
| 1.24.2.6 |
| 21-Jan-2008 |
yamt | sync with head
|
| 1.24.2.5 |
| 07-Dec-2007 |
yamt | sync with head
|
| 1.24.2.4 |
| 27-Oct-2007 |
yamt | sync with head.
|
| 1.24.2.3 |
| 03-Sep-2007 |
yamt | sync with head.
|
| 1.24.2.2 |
| 30-Dec-2006 |
yamt | sync with head.
|
| 1.24.2.1 |
| 21-Jun-2006 |
yamt | sync with head.
|
| 1.26.8.1 |
| 11-Aug-2006 |
yamt | sync with head
|
| 1.26.4.1 |
| 09-Sep-2006 |
rpaulo | sync with head
|
| 1.27.6.1 |
| 10-Dec-2006 |
yamt | sync with head.
|
| 1.27.4.1 |
| 18-Nov-2006 |
ad | Sync with head.
|
| 1.28.16.7 |
| 11-Oct-2007 |
garbled | Fix the NOTICE: curlwp should be set before main() on OEA machines.
|
| 1.28.16.6 |
| 11-Oct-2007 |
garbled | Move a bunch of the macppc SMP code out of macppc, and down into the
generic OEA code. Add a set of md callbacks into these shared routines,
that any oeappc SMP machine needs to provide. This allows for generally
shared SMP startup code, but still allows for machine-specific
differences in the setup and kicking of the new CPU.
Convert macppc to this new layout. Tested by Macallan.
Add an initial attempt at SMP to prep. Tested on UP machine only,
untested on SMP yet.
|
| 1.28.16.5 |
| 04-Oct-2007 |
macallan | add event counters for IPIs received on each CPU
|
| 1.28.16.4 |
| 03-Oct-2007 |
garbled | Sync with HEAD
|
| 1.28.16.3 |
| 02-Aug-2007 |
macallan | sync with HEAD
|
| 1.28.16.2 |
| 26-Jun-2007 |
garbled | Sync with HEAD.
|
| 1.28.16.1 |
| 22-May-2007 |
matt | Update to HEAD.
|
| 1.28.10.1 |
| 11-Jul-2007 |
mjf | Sync with head.
|
| 1.28.8.5 |
| 03-Dec-2007 |
ad | Sync with HEAD.
|
| 1.28.8.4 |
| 23-Oct-2007 |
ad | Sync with head.
|
| 1.28.8.3 |
| 15-Jul-2007 |
ad | Sync with head.
|
| 1.28.8.2 |
| 09-Jun-2007 |
ad | Sync with head.
|
| 1.28.8.1 |
| 27-May-2007 |
ad | Sync with head.
|
| 1.28.4.1 |
| 03-Apr-2007 |
matt | Adapt powerpc to yamt-idlelwp. Nuke cpu_setfunc.
Don't define _HAVE_BITENDIAN_BITOPS. Misc cleanups.
|
| 1.32.14.2 |
| 18-Nov-2007 |
bouyer | Sync with HEAD
|
| 1.32.14.1 |
| 25-Oct-2007 |
bouyer | Sync with HEAD.
|
| 1.32.12.1 |
| 18-Oct-2007 |
yamt | sync with head.
|
| 1.32.10.3 |
| 23-Mar-2008 |
matt | sync with HEAD
|
| 1.32.10.2 |
| 09-Jan-2008 |
matt | sync with HEAD
|
| 1.32.10.1 |
| 06-Nov-2007 |
matt | sync with HEAD
|
| 1.32.8.2 |
| 21-Nov-2007 |
joerg | Sync with HEAD.
|
| 1.32.8.1 |
| 26-Oct-2007 |
joerg | Sync with HEAD.
Follow the merge of pmap.c on i386 and amd64 and move
pmap_init_tmp_pgtbl into arch/x86/x86/pmap.c. Modify the ACPI wakeup
code to restore CR4 before jumping back into kernel space as the large
page option might cover that.
|
| 1.33.2.2 |
| 18-Feb-2008 |
mjf | Sync with HEAD.
|
| 1.33.2.1 |
| 19-Nov-2007 |
mjf | Sync with HEAD.
|
| 1.35.6.2 |
| 19-Jan-2008 |
bouyer | Sync with HEAD
|
| 1.35.6.1 |
| 02-Jan-2008 |
bouyer | Sync with HEAD
|
| 1.44.6.5 |
| 17-Jan-2009 |
mjf | Sync with HEAD.
|
| 1.44.6.4 |
| 05-Oct-2008 |
mjf | Sync with HEAD.
|
| 1.44.6.3 |
| 28-Sep-2008 |
mjf | Sync with HEAD.
|
| 1.44.6.2 |
| 02-Jun-2008 |
mjf | Sync with HEAD.
|
| 1.44.6.1 |
| 03-Apr-2008 |
mjf | Sync with HEAD.
|
| 1.44.2.1 |
| 24-Mar-2008 |
keiichi | sync with head.
|
| 1.46.6.2 |
| 10-Oct-2008 |
skrll | Sync with HEAD.
|
| 1.46.6.1 |
| 23-Jun-2008 |
wrstuden | Sync w/ -current. 34 merge conflicts to follow.
|
| 1.46.4.2 |
| 11-Mar-2010 |
yamt | sync with head
|
| 1.46.4.1 |
| 04-May-2009 |
yamt | sync with head.
|
| 1.46.2.1 |
| 04-Jun-2008 |
yamt | sync with head
|
| 1.47.4.1 |
| 19-Oct-2008 |
haad | Sync with HEAD.
|
| 1.50.14.4 |
| 12-Feb-2011 |
matt | Add IBM750GX support (from Bob Lee).
|
| 1.50.14.3 |
| 28-Jan-2011 |
matt | IBM750FX has HIGHBAT (BATs >= 4)
|
| 1.50.14.2 |
| 17-Jan-2011 |
matt | Add SPE (signal processing engine) support for mpc85xx/booke. Think of it
as AltiVec-lite (really lite). Genercize AltiVec support so that it could
the same interface could support SPE as well. Rework the FPU support along
the same lines. Move the __asm() to their own XXX_subr.S (altivec, fpu, spe).
|
| 1.50.14.1 |
| 07-Jan-2011 |
matt | Deal with new powerpc world.
|
| 1.50.2.2 |
| 28-Apr-2009 |
skrll | Sync with HEAD.
|
| 1.50.2.1 |
| 19-Jan-2009 |
skrll | Sync with HEAD.
|
| 1.51.2.1 |
| 13-May-2009 |
jym | Sync with HEAD.
Commit is split, to avoid a "too many arguments" protocol error.
|
| 1.54.2.4 |
| 06-Nov-2010 |
uebayasi | Sync with HEAD.
|
| 1.54.2.3 |
| 22-Oct-2010 |
uebayasi | Sync with HEAD (-D20101022).
|
| 1.54.2.2 |
| 27-May-2010 |
uebayasi | Fix build.
|
| 1.54.2.1 |
| 30-Apr-2010 |
uebayasi | Sync with HEAD.
|
| 1.55.2.2 |
| 12-Jun-2011 |
rmind | sync with head
|
| 1.55.2.1 |
| 05-Mar-2011 |
rmind | sync with head
|
| 1.59.2.1 |
| 06-Jun-2011 |
jruoho | Sync with HEAD.
|
| 1.61.2.1 |
| 17-Feb-2011 |
bouyer | Sync with HEAD
|
| 1.62.2.1 |
| 23-Jun-2011 |
cherry | Catchup with rmind-uvmplock merge.
|
| 1.70.6.1 |
| 18-Feb-2012 |
mrg | merge to -current.
|
| 1.70.2.3 |
| 22-May-2014 |
yamt | sync with head.
for a reference, the tree before this commit was tagged
as yamt-pagecache-tag8.
this commit was splitted into small chunks to avoid
a limitation of cvs. ("Protocol error: too many arguments")
|
| 1.70.2.2 |
| 30-Oct-2012 |
yamt | sync with head
|
| 1.70.2.1 |
| 17-Apr-2012 |
yamt | sync with head
|
| 1.73.6.3 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.73.6.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.73.6.1 |
| 20-Nov-2012 |
tls | Resync to 2012-11-19 00:00:00 UTC
|
| 1.76.2.1 |
| 18-May-2014 |
rmind | sync with head
|
| 1.82.6.1 |
| 28-Aug-2017 |
skrll | Sync with HEAD
|
| 1.90.2.4 |
| 18-Jan-2019 |
pgoyette | Synch with HEAD
|
| 1.90.2.3 |
| 25-Jun-2018 |
pgoyette | Sync with HEAD
|
| 1.90.2.2 |
| 21-May-2018 |
pgoyette | Sync with HEAD
|
| 1.90.2.1 |
| 30-Mar-2018 |
pgoyette | Resolve conflicts between branch and HEAD
|
| 1.97.2.2 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.97.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.104.2.1 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
| 1.107.2.1 |
| 03-Apr-2021 |
thorpej | Sync with HEAD.
|
| 1.108.16.2 |
| 22-Feb-2025 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #1057):
distrib/utils/embedded/conf/evbppc.conf: revision 1.4
sys/arch/powerpc/oea/cpu_subr.c: revision 1.111
sys/arch/evbppc/wii/pic_pi.c: revision 1.2
sys/arch/evbppc/conf/WII: revision 1.9
sys/arch/evbppc/wii/dev/bwai.c: revision 1.4
wii: Simplify Processor Interface pic code.
wii: Audio playback improvements.
Instead of resetting the byte counter for every block (which is racy),
increment the interrupt timing register by the exact byte count for
each block. Should do better at keeping things in sync.
powerpc: Identify Broadway CPU.
Use hex to report Broadway revision and ignore TAU as it does not exist
on this processor.
wii: Remove some options to save memory.
wii: Disable ntpd by default.
It takes up a lot of memory.
|
| 1.108.16.1 |
| 03-Feb-2024 |
martin | Pull up following revision(s) (requested by jmcneill in ticket #561):
etc/etc.evbppc/Makefile.inc: revision 1.15
sys/arch/evbppc/wii/dev/wiifb.c: revision 1.1
sys/arch/evbppc/wii/dev/wiifb.c: revision 1.2
sys/arch/evbppc/wii/dev/bwdsp.c: revision 1.1
sys/arch/evbppc/wii/dev/wiifb.c: revision 1.3
sys/arch/evbppc/wii/dev/bwdsp.c: revision 1.2
distrib/utils/embedded/files/evbppc_wii_icon.png: revision 1.1
usr.sbin/sysinst/arch/evbppc/md.h: revision 1.4
sys/arch/evbppc/wii/dev/wiifb.c: revision 1.4
sys/arch/evbppc/wii/dev/viio.h: revision 1.1
sys/arch/evbppc/wii/dev/wiifb.c: revision 1.5
sys/arch/evbppc/wii/dev/mainbus.h: revision 1.1
distrib/utils/embedded/conf/wii.conf: revision 1.1
distrib/utils/embedded/conf/wii.conf: revision 1.2
distrib/utils/embedded/conf/wii.conf: revision 1.3
sys/dev/sdmmc/sdhcvar.h: revision 1.34
sys/dev/sdmmc/sdhc.c: revision 1.118
sys/arch/evbppc/wii/dev/resetbtn.c: revision 1.1
distrib/utils/embedded/conf/evbppc.conf: revision 1.1
sys/dev/wsfb/genfb.c: revision 1.91
sys/arch/evbppc/wii/dev/resetbtn.c: revision 1.2
sys/dev/wscons/wsconsio.h: revision 1.127
sys/arch/powerpc/oea/oea_machdep.c: revision 1.85
sys/arch/evbppc/wii/dev/hollywood.h: revision 1.1
sys/arch/evbppc/conf/std.wii: revision 1.1
sys/arch/evbppc/wii/dev/hollywood.h: revision 1.2
sys/arch/evbppc/wii/dev/hollywood.c: revision 1.1
sys/arch/evbppc/conf/std.wii: revision 1.2
sys/arch/evbppc/wii/dev/hollywood.c: revision 1.2
sys/arch/evbppc/conf/std.wii: revision 1.3
sys/arch/powerpc/oea/cpu_subr.c: revision 1.109
sys/arch/evbppc/wii/wii_mmuinit.S: revision 1.1
sys/dev/usb/usb.h: revision 1.124
sys/arch/evbppc/wii/machdep.c: revision 1.1
sys/arch/evbppc/wii/dev/rtcsram.c: revision 1.1
sys/arch/powerpc/include/oea/hid.h: revision 1.14
sys/arch/evbppc/wii/mainbus.c: revision 1.1
sys/arch/evbppc/wii/machdep.c: revision 1.2
sys/arch/evbppc/wii/dev/ehci_hollywood.c: revision 1.1
sys/arch/evbppc/wii/mainbus.c: revision 1.2
sys/arch/evbppc/wii/machdep.c: revision 1.3
sys/arch/evbppc/wii/dev/ehci_hollywood.c: revision 1.2
sys/arch/evbppc/wii/mainbus.c: revision 1.3
sys/arch/evbppc/wii/machdep.c: revision 1.4
sys/arch/evbppc/wii/dev/hwgpio.c: revision 1.1
sys/arch/evbppc/wii/dev/sdhc_hollywood.c: revision 1.1
sys/arch/evbppc/wii/dev/sdhc_hollywood.c: revision 1.2
sys/arch/evbppc/wii/wii_locore.S: revision 1.1
sys/arch/evbppc/conf/files.wii: revision 1.1
sys/arch/evbppc/wii/wii_locore.S: revision 1.2
sys/arch/evbppc/include/wii.h: revision 1.1
sys/arch/evbppc/conf/files.wii: revision 1.2
sys/arch/evbppc/wii/dev/exi.c: revision 1.1
sys/arch/evbppc/include/wii.h: revision 1.2
sys/arch/evbppc/conf/files.wii: revision 1.3
sys/arch/powerpc/powerpc/clock.c: revision 1.18
sys/arch/evbppc/include/wii.h: revision 1.3
sys/arch/evbppc/conf/files.wii: revision 1.4
sys/arch/evbppc/include/wii.h: revision 1.4
sys/arch/evbppc/wii/dev/exi.h: revision 1.1
sys/arch/evbppc/wii/dev/avenc.c: revision 1.1
sys/arch/evbppc/include/wii.h: revision 1.5
sys/arch/evbppc/include/wii.h: revision 1.6
sys/arch/evbppc/include/wii.h: revision 1.7
sys/arch/evbppc/wii/dev/avenc.h: revision 1.1
distrib/utils/embedded/mkimage: revision 1.79
sys/arch/evbppc/conf/WII: revision 1.1
sys/arch/evbppc/conf/INSTALL_WII: revision 1.1
distrib/utils/embedded/files/evbppc_wii_meta.xml: revision 1.1
sys/arch/evbppc/wii/dev/vireg.h: revision 1.1
sys/arch/evbppc/conf/WII: revision 1.2
distrib/utils/embedded/files/evbppc_wii_meta.xml: revision 1.2
sys/arch/evbppc/wii/dev/vireg.h: revision 1.2
sys/arch/evbppc/conf/WII: revision 1.3
sys/arch/evbppc/conf/WII: revision 1.4
usr.sbin/sysinst/arch/evbppc/md.c: revision 1.11
sys/arch/evbppc/wii/dev/ohci_hollywood.c: revision 1.1
sys/dev/usb/ehcivar.h: revision 1.52
sys/arch/evbppc/wii/pic_pi.c: revision 1.1
sys/arch/evbppc/wii/dev/ohci_hollywood.c: revision 1.2
etc/etc.evbppc/ttys: revision 1.8
sys/arch/evbppc/wii/dev/bwai.c: revision 1.1
sys/arch/evbppc/wii/dev/bwai.c: revision 1.2
sys/arch/evbppc/wii/dev/bwai.c: revision 1.3
sys/arch/evbppc/wii/autoconf.c: revision 1.1
sys/arch/evbppc/conf/Makefile.wii.inc: revision 1.1
sys/arch/evbppc/wii/dev/bwai.h: revision 1.1
sys/arch/evbppc/wii/autoconf.c: revision 1.2
sys/arch/evbppc/conf/Makefile.wii.inc: revision 1.2
powerpc: oea: Fix prefetchable mappings
Prefetchable mappings need PMAP_NOCACHE to get write-combine semantics.
powerpc: oea: Decode IBM750CL L2 cache information.
sdmmc: add support for optional delay after register write
wscons: Add HOLLYWOOD display and YUY2 pixel format types
wsfb: add support for optional "devcmap" property
A hardware driver can supply a pointer to a 16x 32-bit array to override
the default rasops device colour map in the "devcmap" property.
ehci: add EHCIF_32BIT_ACCESS flag to force 32-bit MMIO
fix comments: HID0 ICFI/DCFI are "flash invalidate", not "flush invalidate"
powerpc: fix delay for large (> ~5sec) values
When calculating the target timebase, promote '1000' on the RHS to ULL
to force 64-bit calculation, otherwise 'n * 1000' will overflow.
usb: increase USB_PORT_RESET_RECOVERY from 10ms to 20ms
I changed this from 250ms to 10ms back in 2021 based on a similar FreeBSD
change, but it seems to be a bit too aggressive for some platforms.
evbppc: Add initial support for the Nintendo Wii
wii: support RB_POWERDOWN
build fix: use dd with count=1 for compat with NetBSD dd(1)
wii: Add NTSC 480p support.
In addition to this, add VIIO_{GET,SET}REGS ioctl support to allow for
poking at video interface registers from userland. This is helpful for
debugging display issues.
wii: Add 128x48 icon to SD card image
wii: Fix a comment
wii: Add drivers for Broadway DSP and Audio interface.
0: [*] audio0 @ bwdsp0: Broadway DSP
playback: 16, 2ch, 48000Hz
record: unavailable
(P-) slinear_be 16/16, 2ch, { 48000 }
wii: Add screenblank support.
wii: Use screen dimming register for screen blanking.
wii: Add GPIO, I2C, and basic A/V encoder driver.
wii: Use A/V encoder volume controls instead of using a software filter.
wii: Simply DSP driver - no interrupt handler required.
wii: provide device names to intr_establish
wii$ intrctl list
interrupt id CPU0 device name(s)
pi irq 14 64769* hollywood0
hollywood irq 36 5872* ehci0
hollywood irq 39 58907* sdhc0
hollywood irq 40 4* sdhc1
hollywood irq 49 0* resetbtn0
pi irq 5 0* bwai0
wii: Add support for passing boot options to the kernel.
wii: Add External interface bus and RTC support
wii: Remove objcopy after kernel build.
HBC will do the right thing.
Add wsvt25 entries (off by default) for ttyE0-ttyE3.
Add support for "PAL" (576i) mode on Wii.
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