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    Searched refs:RLC_LB_CNTL (Results 1 - 7 of 7) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v9_0.c 1751 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1752 * but used for RLC_LB_CNTL configuration */
1754 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1755 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1800 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
1801 * but used for RLC_LB_CNTL configuration */
1803 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
1804 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
1813 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
sid.h 1335 #define RLC_LB_CNTL 0x30C3
amdgpu_gfx_v6_0.c 2436 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
cikd.h 1405 #define RLC_LB_CNTL 0xC364
sid.h 1306 #define RLC_LB_CNTL 0xC30C
radeon_si.c 5859 tmp = RREG32(RLC_LB_CNTL);
5864 WREG32(RLC_LB_CNTL, tmp);
5889 WREG32(RLC_LB_CNTL, 0);
radeon_cik.c 5801 tmp = RREG32(RLC_LB_CNTL);
5806 WREG32(RLC_LB_CNTL, tmp);
5962 WREG32(RLC_LB_CNTL, 0x80000004);

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