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    Searched refs:RLC_PG_CNTL (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cik.c 6385 orig = data = RREG32(RLC_PG_CNTL);
6391 WREG32(RLC_PG_CNTL, data);
6399 orig = data = RREG32(RLC_PG_CNTL);
6405 WREG32(RLC_PG_CNTL, data);
6412 orig = data = RREG32(RLC_PG_CNTL);
6418 WREG32(RLC_PG_CNTL, data);
6425 orig = data = RREG32(RLC_PG_CNTL);
6431 WREG32(RLC_PG_CNTL, data);
6528 orig = data = RREG32(RLC_PG_CNTL);
6531 WREG32(RLC_PG_CNTL, data)
    [all...]
cikd.h 1427 #define RLC_PG_CNTL 0xC40C
sid.h 1328 #define RLC_PG_CNTL 0xC35C
radeon_si.c 5270 tmp = RREG32(RLC_PG_CNTL);
5272 WREG32(RLC_PG_CNTL, tmp);
5292 tmp = RREG32(RLC_PG_CNTL);
5294 WREG32(RLC_PG_CNTL, tmp);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfx_v8_0.c 4042 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PU_ENABLE, enable ? 1 : 0);
4048 WREG32_FIELD(RLC_PG_CNTL, SMU_CLK_SLOWDOWN_ON_PD_ENABLE, enable ? 1 : 0);
4053 WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
5340 WREG32_FIELD(RLC_PG_CNTL, STATIC_PER_CU_PG_ENABLE, enable ? 1 : 0);
5346 WREG32_FIELD(RLC_PG_CNTL, DYN_PER_CU_PG_ENABLE, enable ? 1 : 0);
5352 WREG32_FIELD(RLC_PG_CNTL, QUICK_PG_ENABLE, enable ? 1 : 0);
5358 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, enable ? 1 : 0);
5364 WREG32_FIELD(RLC_PG_CNTL, GFX_PIPELINE_PG_ENABLE, enable ? 1 : 0);
amdgpu_gfx_v9_0.c 2805 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2819 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2833 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2846 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2859 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2876 data = REG_SET_FIELD(data, RLC_PG_CNTL,
2889 data = REG_SET_FIELD(data, RLC_PG_CNTL,
amdgpu_gfx_v6_0.c 2780 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2833 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
sid.h 1357 #define RLC_PG_CNTL 0x30D7

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