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    Searched refs:RO (Results 1 - 25 of 31) sorted by relevancy

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  /src/external/bsd/ntp/dist/libparse/
info_trimble.c 58 { CMD_RDATAA, "CMD_RDATAA", "data channel A configuration (0x3D)", "trimble_channelA", RO },
59 { CMD_RALMANAC, "CMD_RALMANAC", "almanac data for sat (0x40)", "gps_almanac", RO },
60 { CMD_RCURTIME, "CMD_RCURTIME", "GPS time (0x41)", "gps_time", RO },
61 { CMD_RSPOSXYZ, "CMD_RSPOSXYZ", "single precision XYZ position (0x42)", "gps_position(XYZ)", RO|DEF },
62 { CMD_RVELOXYZ, "CMD_RVELOXYZ", "velocity fix (XYZ ECEF) (0x43)", "gps_velocity(XYZ)", RO|DEF },
63 { CMD_RBEST4, "CMD_RBEST4", "best 4 satellite selection (0x44)", "trimble_best4", RO|DEF },
64 { CMD_RVERSION, "CMD_RVERSION", "software version (0x45)", "trimble_version", RO|DEF },
65 { CMD_RRECVHEALTH, "CMD_RRECVHEALTH", "receiver health (0x46)", "trimble_receiver_health", RO|DEF },
66 { CMD_RSIGNALLV, "CMD_RSIGNALLV", "signal levels of all satellites (0x47)", "trimble_signal_levels", RO },
67 { CMD_RMESSAGE, "CMD_RMESSAGE", "GPS system message (0x48)", "gps-message", RO|DEF }
    [all...]
  /src/external/bsd/ntp/dist/ntpd/
ntp_control.c 348 { CS_STRATUM, RO, "stratum" }, /* 2 */
349 { CS_PRECISION, RO, "precision" }, /* 3 */
350 { CS_ROOTDELAY, RO, "rootdelay" }, /* 4 */
351 { CS_ROOTDISPERSION, RO, "rootdisp" }, /* 5 */
352 { CS_REFID, RO, "refid" }, /* 6 */
353 { CS_REFTIME, RO, "reftime" }, /* 7 */
354 { CS_POLL, RO, "tc" }, /* 8 */
355 { CS_PEERID, RO, "peer" }, /* 9 */
356 { CS_OFFSET, RO, "offset" }, /* 10 */
357 { CS_DRIFT, RO, "frequency" }, /* 11 *
    [all...]
refclock_neoclock4x.c 741 tt = add_var(&out->kv_list, sizeof(tmpbuf)-1, RO|DEF);
744 tt = add_var(&out->kv_list, 40, RO|DEF);
746 tt = add_var(&out->kv_list, 40, RO|DEF);
748 tt = add_var(&out->kv_list, 40, RO|DEF);
750 tt = add_var(&out->kv_list, 40, RO|DEF);
757 tt = add_var(&out->kv_list, 40, RO|DEF);
764 tt = add_var(&out->kv_list, 40, RO|DEF);
772 tt = add_var(&out->kv_list, 80, RO|DEF);
774 tt = add_var(&out->kv_list, 40, RO|DEF);
776 tt = add_var(&out->kv_list, 80, RO|DEF)
    [all...]
refclock_parse.c 3575 tt = add_var(&out->kv_list, 80, RO);
3582 tt = add_var(&out->kv_list, 80, RO|DEF);
3586 start = tt = add_var(&out->kv_list, 128, RO|DEF);
3606 start = tt = add_var(&out->kv_list, 512, RO|DEF);
3640 start = tt = add_var(&out->kv_list, 80, RO|DEF);
3657 start = tt = add_var(&out->kv_list, LEN_STATES, RO|DEF);
3701 tt = add_var(&out->kv_list, 32, RO);
3704 tt = add_var(&out->kv_list, 80, RO);
3707 tt = add_var(&out->kv_list, 128, RO);
4362 set_var(&parse->kv, buffer, strlen(buffer)+1, RO|DEF)
    [all...]
  /src/sys/dev/microcode/aic7xxx/
aic79xx.reg 225 access_mode RO
299 access_mode RO
442 access_mode RO
467 access_mode RO
648 access_mode RO
659 access_mode RO
670 access_mode RO
696 access_mode RO
706 access_mode RO
716 access_mode RO
    [all...]
aic7xxx.reg 108 access_mode RO
281 access_mode RO
314 access_mode RO
330 access_mode RO
346 access_mode RO
423 access_mode RO
633 access_mode RO
639 access_mode RO
651 access_mode RO
658 access_mode RO
    [all...]
aicasm_symbol.h 69 RO = 0x01,
aicasm_scan.l 171 RW|RO|WO {
174 else if (strcmp(yytext, "RO") == 0)
175 yylval.value = RO;
aicasm_gram.y 1809 if (symbol->info.rinfo->mode == RO) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
CFIInstrInserter.cpp 365 CSRSavedLocation RO = it->second;
366 if (!RO.Reg && RO.Offset) {
368 MCCFIInstruction::createOffset(nullptr, Reg, *RO.Offset));
369 } else if (RO.Reg && !RO.Offset) {
371 MCCFIInstruction::createRegister(nullptr, Reg, *RO.Reg));
373 llvm_unreachable("RO.Reg and RO.Offset cannot both be valid/invalid");
  /src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/
MCDisassembler.cpp 53 SMC_PCASE(RO, 1)
  /src/external/bsd/pcc/dist/pcc/cc/cxxcom/
optim.c 41 # define RO(p) p->n_right->n_op
181 if (RO(p) == ICON) {
223 if (RO(p) == ICON) {
289 if( RO(p) == o ){
397 if (RO(p) != NE)
  /src/external/bsd/pcc/dist/pcc/cc/ccom/
optim.c 45 # define RO(p) p->n_right->n_op
185 if (RO(p) == ICON) {
225 if (RO(p) == ICON) {
303 if( RO(p) == o ){
443 if (RO(p) != NE)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonEarlyIfConv.cpp 820 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1);
822 SR = RO.getReg(), SSR = RO.getSubReg();
824 TR = RO.getReg(), TSR = RO.getSubReg();
826 FR = RO.getReg(), FSR = RO.getSubReg();
HexagonGenInsert.cpp 387 OrderedRegisterList(const RegisterOrdering &RO)
388 : MaxSize(MaxORLSize), Ord(RO) {}
529 void buildOrderingMF(RegisterOrdering &RO) const;
530 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
597 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {
617 RO.insert(std::make_pair(R, Index++));
628 RegisterOrdering &RO) const {
642 RO.insert(std::make_pair(VRs[i], i));
HexagonExpandCondsets.cpp 230 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
906 /// In the range [First, Last], rename all references to the "old" register RO
909 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
923 if (!Op.isReg() || RO != RegisterRef(Op))
HexagonInstrInfo.cpp 650 const MachineOperand &RO = Cond[1];
651 unsigned Flags = getUndefRegState(RO.isUndef());
652 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
674 const MachineOperand &RO = Cond[1];
675 unsigned Flags = getUndefRegState(RO.isUndef());
676 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
X86WinCOFFTargetStreamer.cpp 351 for (RegSaveOffset RO : RegSaveOffsets)
352 FuncOS << printFPOReg(MRI, RO.Reg) << ' ' << CFAVar << ' ' << RO.Offset
  /src/external/apache2/llvm/dist/llvm/lib/BinaryFormat/
XCOFF.cpp 21 SMC_CASE(RO)
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CodeGenFunction.cpp 2517 CodeGenFunction::FormResolverCondition(const MultiVersionResolverOption &RO) {
2520 if (!RO.Conditions.Architecture.empty())
2521 Condition = EmitX86CpuIs(RO.Conditions.Architecture);
2523 if (!RO.Conditions.Features.empty()) {
2524 llvm::Value *FeatureCond = EmitX86CpuSupports(RO.Conditions.Features);
2566 for (const MultiVersionResolverOption &RO : Options) {
2568 llvm::Value *Condition = FormResolverCondition(RO);
2572 assert(&RO == Options.end() - 1 &&
2574 CreateMultiVersionResolverReturn(CGM, Resolver, Builder, RO.Function,
2581 CreateMultiVersionResolverReturn(CGM, Resolver, RetBuilder, RO.Function
    [all...]
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
AsmWriterEmitter.cpp 894 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i];
896 switch (RO.Kind) {
898 const Record *Rec = RO.getRecord();
899 StringRef ROName = RO.getName();
982 MIOpNum += RO.getMINumOperands();
  /src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/
RegionStore.cpp 116 const RegionOffset &RO = R->getAsOffset();
117 if (RO.hasSymbolicOffset())
118 return BindingKey(cast<SubRegion>(R), cast<SubRegion>(RO.getRegion()), k);
120 return BindingKey(RO.getRegion(), RO.getOffset(), k);
1186 const RegionOffset &RO = baseR->getAsOffset();
1188 if (RO.hasSymbolicOffset()) {
1196 uint64_t LowerOffset = RO.getOffset();
  /src/external/apache2/llvm/dist/llvm/tools/llvm-diff/
DifferenceEngine.cpp 371 Value *LO = L->getOperand(I), *RO = R->getOperand(I);
372 if (!equivalentAsOperands(LO, RO)) {
373 if (Complain) Engine.logf("operands %l and %r differ") << LO << RO;
  /src/external/bsd/ntp/dist/include/
ntpd.h 106 #define RO (CAN_READ)
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
ModuleSummaryIndex.h 212 // We expect ro/wo attribute to set only once during
880 void setReadOnly(bool RO) { VarFlags.MaybeReadOnly = RO; }

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