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    Searched refs:RegSize (Results 1 - 25 of 29) sorted by relevancy

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  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFrameLowering.cpp 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
128 Size = alignTo(Size + RegSize, RegSize);
MipsCallLowering.cpp 470 unsigned RegSize = 4;
472 VaArgOffset = alignTo(CCInfo.getNextStackOffset(), RegSize);
476 (int)(RegSize * (ArgRegs.size() - Idx));
480 int FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
483 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) {
487 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I]));
488 FI = MFI.CreateFixedObject(RegSize, VaArgOffset, true);
493 MPO, MachineMemOperand::MOStore, RegSize, Align(RegSize));
MipsSEFrameLowering.cpp 78 void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
80 unsigned MFLoOpc, unsigned RegSize);
198 unsigned RegSize) {
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
217 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize);
223 unsigned RegSize) {
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
241 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize);
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
InfoByHwMode.cpp 120 RegSize = R->getValueAsInt("RegSize");
126 return std::tie(RegSize, SpillSize, SpillAlignment) <
127 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
131 return RegSize <= I.RegSize &&
137 OS << "[R=" << RegSize << ",S=" << SpillSize
InfoByHwMode.h 149 unsigned RegSize;
157 return std::tie(RegSize, SpillSize, SpillAlignment) ==
158 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
RegisterInfoEmitter.cpp 1080 uint32_t RegSize = 0;
1082 RegSize = RC.RSI.getSimple().RegSize;
1087 << ", " << RegSize << ", " << RC.CopyCost << ", "
1289 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", "
CodeGenRegisters.cpp 792 RI.RegSize = RI.SpillSize = Size ? Size
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86TileConfig.cpp 174 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R));
175 if ((IsRow && RegSize == 8) || (!IsRow && RegSize == 16))
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/
DwarfExpression.cpp 138 unsigned RegSize = TRI.getRegSizeInBits(*RC);
144 SmallBitVector Coverage(RegSize, false);
155 SmallBitVector CurSubReg(RegSize, false);
179 if (CurPos < RegSize)
181 -1, RegSize - CurPos, "no DWARF register encoding"));
  /src/external/apache2/llvm/dist/clang/lib/Basic/Targets/
X86.h 202 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
208 HasSizeMismatch = RegSize != 32;
742 bool validateGlobalRegisterVariable(StringRef RegName, unsigned RegSize,
748 HasSizeMismatch = RegSize != 64;
753 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize,
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64AddressingModes.h 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize,
216 (RegSize != 64 &&
217 (Imm >> RegSize != 0 || Imm == (~0ULL >> (64 - RegSize)))))
221 unsigned Size = RegSize;
275 static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) {
277 return processLogicalImmediate(imm, regSize, encoding);
282 static inline uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize) {
284 bool res = processLogicalImmediate(imm, regSize, encoding);
292 /// integer value it represents with regSize bits
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
TargetRegisterInfo.cpp 511 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0;
514 if (RegSize)
515 return RegSize;
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetRegisterInfo.h 236 unsigned RegSize, SpillSize, SpillAlignment;
275 return getRegClassInfo(RC).RegSize;
  /src/sys/external/bsd/acpica/dist/common/
dmtbinfo1.c 1268 {ACPI_DMT_UINT32, ACPI_ERDT_MMRC_OFFSET (RegSize), "MBM Register Size", 0},
1329 {ACPI_DMT_UINT32, ACPI_ERDT_CMRD_OFFSET (RegSize), "CMRD Register Size", 0},
1350 {ACPI_DMT_UINT32, ACPI_ERDT_IBRD_OFFSET (RegSize), "IBRD Register Size", 0},
1395 {ACPI_DMT_UINT32, ACPI_ERDT_CARD_OFFSET (RegSize), "CARD Register Size", 0},
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZInstrInfo.cpp 904 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
905 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
907 explicit operator bool() const { return RegSize; }
909 unsigned RegSize = 0;
954 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
956 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
958 if (And.RegSize == 64) {
  /src/sys/external/bsd/acpica/dist/include/
actbl2.h 663 UINT32 RegSize;
710 UINT32 RegSize;
728 UINT32 RegSize;
762 UINT32 RegSize;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFrameLowering.cpp 264 int RegSize;
267 RegSize = 8;
271 RegSize = 4;
284 count += RegSize;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64FastISel.cpp 1652 unsigned RegSize;
1663 RegSize = 32;
1669 RegSize = 64;
1673 if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))
1678 AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
4022 unsigned RegSize = Is64Bit ? 64 : 32;
4069 unsigned ImmR = RegSize - Shift;
4125 unsigned RegSize = Is64Bit ? 64 : 32;
4173 return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
4241 unsigned RegSize = Is64Bit ? 64 : 32
    [all...]
AArch64FrameLowering.cpp 2802 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8;
2805 SVECSStackSize += RegSize;
2807 CSStackSize += RegSize;
  /src/external/apache2/llvm/dist/clang/include/clang/Basic/
TargetInfo.h 1043 /// variable size passed in RegSize.
1045 unsigned RegSize,
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
TargetInfo.cpp 4774 CharUnits RegSize = CharUnits::fromQuantity((isInt || IsSoftFloatABI) ? 4 : 8);
4776 Builder.CreateMul(NumRegs, Builder.getInt8(RegSize.getQuantity()));
4779 RegAddr.getAlignment().alignmentOfArrayElement(RegSize));
5913 int RegSize = IsIndirect ? 8 : TySize.getQuantity();
5919 RegSize = llvm::alignTo(RegSize, 8);
5925 RegSize = 16 * NumRegs;
5966 reg_offs, llvm::ConstantInt::get(CGF.Int32Ty, RegSize), "new_reg_offs");
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPULegalizerInfo.cpp 269 unsigned RegSize = Ty.getSizeInBits();
287 if (MemSize != RegSize && RegSize != 32)
312 assert(RegSize >= MemSize);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp 860 unsigned RegSize = RegVT.getSizeInBits();
861 assert(RegSize == 32 || RegSize == 64 ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64InstructionSelector.cpp 4203 unsigned RegSize = Ty.getSizeInBits();
4204 bool Is32Bit = (RegSize == 32);
4213 if (AArch64_AM::isLogicalImmediate(Imm, RegSize)) {
4215 TstMI.addImm(AArch64_AM::encodeLogicalImmediate(Imm, RegSize));
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
LegalizerHelper.cpp 160 unsigned RegSize = RegTy.getSizeInBits();
162 unsigned NumParts = RegSize / MainSize;
163 unsigned LeftoverSize = RegSize - NumParts * MainSize;
189 for (unsigned Offset = MainSize * NumParts; Offset < RegSize;

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