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    Searched refs:SCI_CSR_PHASE_MATCH (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/arch/amiga/dev/
mlhsc.c 201 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
202 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
203 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
237 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
238 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
239 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
288 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
289 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
290 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
316 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !
    [all...]
wstsc.c 223 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
224 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
225 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
260 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
261 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
262 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
307 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
308 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
309 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
327 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) =
    [all...]
ivsc.c 211 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
212 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
213 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
248 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
249 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
250 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
295 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
296 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
297 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
315 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) =
    [all...]
otgsc.c 204 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
205 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
206 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
251 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
252 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
253 if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
271 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
272 SCI_CSR_PHASE_MATCH && --wait);
scireg.h 141 #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */
sci.c 432 if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH))
479 if (!(*dev->sci_csr & SCI_CSR_PHASE_MATCH))
  /src/sys/arch/mac68k/dev/
sbc.c 135 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
136 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
140 if (((*sc->sci_csr & SCI_CSR_PHASE_MATCH) == 0)
158 if ((*sc->sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
159 == (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
186 if (((*ncr_sc->sci_csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT)
210 if (((csr & ~(SCI_CSR_PHASE_MATCH | SCI_CSR_ATN)) == SCI_CSR_INT) &&
219 else if (((csr & ~SCI_CSR_PHASE_MATCH) == SCI_CSR_INT) &&
222 else if (((csr & ~(SCI_CSR_DREQ | SCI_CSR_ATN | SCI_CSR_ACK)) == (SCI_CSR_PERR | SCI_CSR_INT | SCI_CSR_PHASE_MATCH)) &&
228 else if (((csr & ~SCI_CSR_PHASE_MATCH) == (SCI_CSR_INT | SCI_CSR_DISC)) &
    [all...]
  /src/sys/arch/mac68k/include/
scsi_5380.h 137 #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */
  /src/sys/dev/podulebus/
hcsc.c 235 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) ==
236 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH))
239 if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
256 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
356 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
oak.c 233 if ((status & (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) ==
234 (SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH))
237 if ((status & SCI_CSR_PHASE_MATCH) == 0 ||
271 (NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
376 & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
  /src/sys/dev/ic/
ncr5380reg.h 156 #define SCI_CSR_PHASE_MATCH 0x08 /* r: Bus and SCI_TCMD match */

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