| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| rv730d.h | 85 #define SCLK_PWRMGT_CNTL 0x644
|
| radeon_rv770_dpm.c | 138 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
140 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
141 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
142 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
177 if (RREG32(SCLK_PWRMGT_CNTL) & DYN_GFX_CLK_OFF_EN)
181 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
186 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
204 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
858 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
860 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL)
[all...] |
| trinityd.h | 177 #define SCLK_PWRMGT_CNTL 0x678
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| radeon_r600_dpm.c | 252 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
254 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
311 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
313 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
366 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
368 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
370 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
372 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
|
| radeon_cypress_dpm.c | 109 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
110 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
111 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
147 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
149 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
151 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
152 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
153 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
157 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
254 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF)
[all...] |
| radeon_sumo_dpm.c | 96 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
98 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
99 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
100 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
446 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
448 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
451 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
454 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
922 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
927 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET)
[all...] |
| radeon_trinity_dpm.c | 451 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
453 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
454 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
455 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
514 WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
516 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN);
778 if (RREG32(SCLK_PWRMGT_CNTL) & DYNAMIC_PM_EN)
809 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~(RESET_SCLK_CNT | RESET_BUSY_CNT));
814 WREG32_P(SCLK_PWRMGT_CNTL, RESET_SCLK_CNT | RESET_BUSY_CNT,
|
| radeon_rv730_dpm.c | 457 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
475 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
|
| sumod.h | 154 #define SCLK_PWRMGT_CNTL 0x644
|
| radeon_ci_dpm.c | 1543 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1545 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1604 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1606 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1627 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1633 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2067 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2069 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2085 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2087 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp)
[all...] |
| radeon_kv_dpm.c | 666 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); local in function:kv_start_am
668 sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
669 sclk_pwrmgt_cntl |= DYNAMIC_PM_EN;
671 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
676 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); local in function:kv_reset_am
678 sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
680 WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl)
[all...] |
| rv770d.h | 160 #define SCLK_PWRMGT_CNTL 0x644
|
| nid.h | 601 #define SCLK_PWRMGT_CNTL 0x644
|
| radeon_si_dpm.c | 3350 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3352 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3781 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3783 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3786 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3789 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
|
| radeon_ni_dpm.c | 1211 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1212 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1213 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
|
| cikd.h | 111 #define SCLK_PWRMGT_CNTL 0xC0200008
|
| sid.h | 253 #define SCLK_PWRMGT_CNTL 0x788
|
| evergreend.h | 139 #define SCLK_PWRMGT_CNTL 0x644
|
| r600d.h | 1309 #define SCLK_PWRMGT_CNTL 0x620
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu7_hwmgr.c | 425 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0);
427 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0);
442 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1);
444 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1);
997 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1158 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
1230 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL,
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 3810 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3812 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
4248 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4250 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4253 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4256 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
|
| sid.h | 255 #define SCLK_PWRMGT_CNTL 0x1e2
|
