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Searched refs:SDMA0_PHASE0_QUANTUM__VALUE_MASK (Results 1 - 13 of 13) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_sdma.c	`361 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 368 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>`
amdgpu_sdma_v3_0.c	`571 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 578 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>`
amdgpu_sdma_v5_0.c	`546 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 553 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>`
amdgpu_sdma_v4_0.c	`1003 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 1010 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_0_sh_mask.h	`602 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L`
sdma0_4_1_sh_mask.h	`601 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L`
sdma0_4_2_2_sh_mask.h	`610 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L`
sdma0_4_2_sh_mask.h	`604 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_0_sh_mask.h	`1015 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00`
oss_2_4_sh_mask.h	`1105 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00`
oss_3_0_1_sh_mask.h	`1125 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00`
oss_3_0_sh_mask.h	`1631 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_sh_mask.h	`316 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L [all...]`

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