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    Searched refs:SDMA0_PHASE0_QUANTUM__VALUE__SHIFT (Results 1 - 13 of 13) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_sdma.c 362 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
369 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
377 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
amdgpu_sdma_v3_0.c 572 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
579 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
587 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
amdgpu_sdma_v5_0.c 547 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
554 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
562 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
amdgpu_sdma_v4_0.c 1004 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
1011 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
1019 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
sdma0_4_0_sh_mask.h 599 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
sdma0_4_1_sh_mask.h 598 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
sdma0_4_2_2_sh_mask.h 607 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
sdma0_4_2_sh_mask.h 601 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
oss_2_0_sh_mask.h 1016 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
oss_2_4_sh_mask.h 1106 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
oss_3_0_1_sh_mask.h 1126 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
oss_3_0_sh_mask.h 1632 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
gc_10_1_0_sh_mask.h 313 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
    [all...]

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