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    Searched refs:SH_ (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/arch/mmeye/stand/boot/
clock.c 40 _reg_write_1(SH_(TOCR), TOCR_TCOE);
41 _reg_write_2(SH_(TCR0), TCR_TPSC_P4);
42 _reg_bset_1(SH_(TSTR), TSTR_STR0);
51 t1 = _reg_read_4(SH_(TCNT0));
53 t2 = _reg_read_4(SH_(TCNT0));
  /src/sys/arch/sh3/sh3/
clock.c 103 _reg_bclr_1(SH_(TSTR), TSTR_STR##x); \
104 _reg_write_4(SH_(TCNT ## x), 0xffffffff); \
105 _reg_bset_1(SH_(TSTR), TSTR_STR##x); \
109 (0xffffffff - _reg_read_4(SH_(TCNT ## x)))
119 _reg_write_2(SH_(TCR0), 0);
120 _reg_write_2(SH_(TCR1), 0);
121 _reg_write_2(SH_(TCR2), 0);
124 _reg_write_1(SH_(RCR1), 0);
127 _reg_write_1(SH_(TSTR), 0);
134 _reg_write_2(SH_(TCR0), TCR_TPSC_P16)
    [all...]
mmu.c 111 _reg_write_4(SH_(PTEH), asid);
sh3_machdep.c 195 _reg_write_2(SH_(BBRA), 0); /* disable channel A */
196 _reg_write_2(SH_(BBRB), 0); /* disable channel B */
558 _reg_write_4(SH_(EXPEVT), EXPEVT_RESET_MANUAL);
interrupt.c 391 printf("INTEVT=0x%x", _reg_read_4(SH_(INTEVT)));
exception.c 158 trapcode = _reg_read_4(SH_(TRA)) >> 2;
  /src/sys/arch/sh3/include/
devreg.h 64 #define SH_(x) __sh_ ## x
66 #define SH_(x) SH3_ ## x
68 #define SH_(x) SH4_ ## x
  /src/sys/arch/sh3/dev/
rtc.c 98 r = _reg_read_1(SH_(RCR2));
115 _reg_write_1(SH_(RCR1), 0);
118 _reg_write_1(SH_(RCR2), SH_RCR2_ENABLE | SH_RCR2_START);
159 _reg_bclr_1(SH_(RCR1), SH_RCR1_CIE);
162 uint8_t r = _reg_read_1(SH_(RCR1));
165 _reg_write_1(SH_(RCR1), r);
175 dt->dt_ ## x = bcdtobin(_reg_read_1(SH_(R ## y ## CNT)))
184 } while ((_reg_read_1(SH_(RCR1)) & SH_RCR1_CF) && --retry > 0);
224 r = _reg_read_1(SH_(RCR2));
227 _reg_write_1(SH_(RCR2), (r & ~SH_RCR2_START) | SH_RCR2_RESET)
    [all...]
  /src/sys/arch/hpc/stand/hpcboot/sh3/
sh_arch.h 80 #define SH_(x) \
113 SH_(7709);
114 SH_(7709A);
115 SH_(7707);
  /src/sys/arch/evbsh3/evbsh3/
machdep.c 378 _reg_write_2(SH_(BCR2), BSC_BCR2_VAL);
443 _reg_write_2(SH_(PCR), BSC_PCR_VAL);
453 _reg_write_2(SH_(RTCSR), BSC_RTCSR_VAL);
460 _reg_write_2(SH_(RTCNT), BSC_RTCNT_VAL);
464 _reg_write_2(SH_(RTCOR), BSC_RTCOR_VAL);
468 _reg_write_2(SH_(RFCR), BSC_RFCR_VAL);
475 _reg_write_2(SH_(FRQCR), FRQCR_VAL);
482 _reg_write_4(SH_(CCR), 0x1);
  /src/sys/arch/mmeye/mmeye/
machdep.c 472 _reg_write_2(SH_(RTCSR), 0xa594);
478 _reg_write_2(SH_(RTCNT), 0xa500);
492 _reg_write_2(SH_(RFCR), 0xa400);
655 evtcode = _reg_read_4(SH_(INTEVT));

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