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Searched refs:SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK (Results 1 - 4 of 4) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
sislands_smc.h	`360 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff`
amdgpu_si_dpm.c	`2990 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 3000 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) \|`
/src/sys/external/bsd/drm2/dist/drm/radeon/
sislands_smc.h	`360 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff`
radeon_si_dpm.c	`2891 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2901 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) \|`

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