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    Searched refs:SMU7_MAX_LEVELS_LINK (Results 1 - 6 of 6) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
smu7.h 46 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
smu7_discrete.h 328 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK];
  /src/sys/external/bsd/drm2/dist/drm/radeon/
smu7.h 46 #define SMU7_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS // PCIe speed and number of lanes.
smu7_discrete.h 327 SMU7_Discrete_LinkLevel LinkLevel [SMU7_MAX_LEVELS_LINK];
radeon_ci_dpm.c 3416 SMU7_MAX_LEVELS_LINK);
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_ci_smumgr.c 2300 return SMU7_MAX_LEVELS_LINK;

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