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  /src/external/gpl3/gdb/dist/sim/ppc/
dc-complex 42 ## Move to/from SPR instructions - LR=8 is munged into 0x100 == 256
44 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256
45 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256
52 ## Move to/from SPR instructions - separate out LR case
54 # Move to SPR
55 array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256
56 # Move from SPR
57 array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256
idecode_fields.h 67 /* the spr field as it normally is used */
69 #define SPR_5_9_ (SPR & 0x1f)
70 #define SPR_0_4_ (SPR >> 5)
71 #define SPR_0_ ((SPR & BIT10(0)) != 0)
powerpc.igen 81 #:compute:::int:SPR_is_256:SPR:(SPR == 256)
136 #define PPC_INSN_FROM_SPR(INT_MASK, SPR) \
139 ppc_insn_from_spr(MY_INDEX, cpu_model(processor), INT_MASK, SPR); \
142 #define PPC_INSN_TO_SPR(INT_MASK, SPR) \
145 ppc_insn_to_spr(MY_INDEX, cpu_model(processor), INT_MASK, SPR); \
187 #define PPC_NO_SPR (-1) /* flag for no SPR register */
200 int16_t spr_busy; /* SPR register that is busy or PPC_NO_SPR */
232 uint8_t spr_busy[nr_of_sprs]; /* SPR registers that are busy */
3346 0.31,6.RS,11.SPR,21.467,31./:XFX::mtspr %SPR, %RS:Move to Special Purpose Registe
    [all...]
gdb-sim.c 31 /* Return the register name for the supplied SPR if any, or NULL if
34 sim_spr_register_name (int spr)
36 if (spr_is_valid (spr))
37 return spr_name (spr);
42 #define regnum2spr(SPR) sim_spr_register_name (SPR)
  /src/external/gpl3/gdb.old/dist/sim/ppc/
dc-complex 42 ## Move to/from SPR instructions - LR=8 is munged into 0x100 == 256
44 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256
45 #array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256
52 ## Move to/from SPR instructions - separate out LR case
54 # Move to SPR
55 array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0003a6:256
56 # Move from SPR
57 array,boolean: 11:20:11:20:SPR: 0xfc0007ff:0x7c0002a6:256
idecode_fields.h 67 /* the spr field as it normally is used */
69 #define SPR_5_9_ (SPR & 0x1f)
70 #define SPR_0_4_ (SPR >> 5)
71 #define SPR_0_ ((SPR & BIT10(0)) != 0)
powerpc.igen 81 #:compute:::int:SPR_is_256:SPR:(SPR == 256)
136 #define PPC_INSN_FROM_SPR(INT_MASK, SPR) \
139 ppc_insn_from_spr(MY_INDEX, cpu_model(processor), INT_MASK, SPR); \
142 #define PPC_INSN_TO_SPR(INT_MASK, SPR) \
145 ppc_insn_to_spr(MY_INDEX, cpu_model(processor), INT_MASK, SPR); \
187 #define PPC_NO_SPR (-1) /* flag for no SPR register */
200 int16_t spr_busy; /* SPR register that is busy or PPC_NO_SPR */
232 uint8_t spr_busy[nr_of_sprs]; /* SPR registers that are busy */
3346 0.31,6.RS,11.SPR,21.467,31./:XFX::mtspr %SPR, %RS:Move to Special Purpose Registe
    [all...]
gdb-sim.c 31 /* Return the register name for the supplied SPR if any, or NULL if
34 sim_spr_register_name (int spr)
36 if (spr_is_valid (spr))
37 return spr_name (spr);
42 #define regnum2spr(SPR) sim_spr_register_name (SPR)
  /src/external/gpl3/binutils/dist/include/opcode/
spu-insns.h 122 SPR SPR/CH pipeline
149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */
150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */
151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */
160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */
161 APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */
335 APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */
  /src/external/gpl3/binutils.old/dist/include/opcode/
spu-insns.h 122 SPR SPR/CH pipeline
149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */
150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */
151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */
160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */
161 APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */
335 APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */
  /src/external/gpl3/gdb.old/dist/include/opcode/
spu-insns.h 122 SPR SPR/CH pipeline
149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */
150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */
151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */
160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */
161 APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */
335 APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */
  /src/external/gpl3/gdb/dist/include/opcode/
spu-insns.h 122 SPR SPR/CH pipeline
149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */
150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */
151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */
160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */
161 APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */
335 APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86PartialReduction.cpp 186 auto SPR = matchSelectPattern(SI, LHS, RHS);
187 if (SPR.Flavor != SPF_ABS)
  /src/external/gpl3/gdb/dist/sim/testsuite/frv/
testutils.inc 69 ; Set GR with SPR
159 ; Set SPR with immediate value
175 ; increment SPR with immediate value
182 ; OR spr with immediate value
190 ; AND spr with immediate value
311 .macro test_spr_gr spr gr
312 movsg \spr,gr28
322 ; Test spr bits masked and shifted against the given value
453 ori gr28,1,gr28 ; Turn on SPR.ET
455 andi gr28,0xfffffffe,gr28 ; Turn off SPR.E
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/testsuite/frv/
testutils.inc 69 ; Set GR with SPR
159 ; Set SPR with immediate value
175 ; increment SPR with immediate value
182 ; OR spr with immediate value
190 ; AND spr with immediate value
311 .macro test_spr_gr spr gr
312 movsg \spr,gr28
322 ; Test spr bits masked and shifted against the given value
453 ori gr28,1,gr28 ; Turn on SPR.ET
455 andi gr28,0xfffffffe,gr28 ; Turn off SPR.E
    [all...]
  /src/external/gpl3/gdb.old/dist/sim/frv/
frv-sim.h 25 /* True if SPR is the number of accumulator or accumulator guard register. */
26 #define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535)
  /src/external/gpl3/gdb/dist/sim/frv/
frv-sim.h 25 /* True if SPR is the number of accumulator or accumulator guard register. */
26 #define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535)
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
LazyValueInfo.cpp 815 SelectPatternResult SPR = matchSelectPattern(SI, LHS, RHS);
818 if (SelectPatternResult::isMinOrMax(SPR.Flavor) &&
821 switch (SPR.Flavor) {
839 if (SPR.Flavor == SPF_ABS) {
848 if (SPR.Flavor == SPF_NABS) {
ValueTracking.cpp 5719 SelectPatternResult SPR = matchClamp(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal);
5720 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN)
5721 return SPR;
5723 SPR = matchMinMaxOfMinMax(Pred, CmpLHS, CmpRHS, TrueVal, FalseVal, Depth);
5724 if (SPR.Flavor != SelectPatternFlavor::SPF_UNKNOWN)
5725 return SPR;
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineSelect.cpp 1049 SelectPatternResult SPR = matchSelectPattern(&Sel, LHS, RHS);
1050 if (!SelectPatternResult::isMinOrMax(SPR.Flavor))
1054 ICmpInst::Predicate CanonicalPred = getMinMaxPred(SPR.Flavor);
2923 SelectPatternResult SPR = matchSelectPattern(&SI, LHS, RHS, &CastOp);
2924 auto SPF = SPR.Flavor;
2951 CmpInst::Predicate MinMaxPred = getMinMaxPred(SPF, SPR.Ordered);
InstCombineCompares.cpp 1364 SelectPatternResult SPR = matchSelectPattern(Cmp.getOperand(0), A, B);
1365 if (SPR.Flavor == SPF_SMIN) {
5641 SelectPatternResult SPR = matchSelectPattern(SI, A, B);
5642 if (SPR.Flavor != SPF_UNKNOWN)
6225 SelectPatternResult SPR = matchSelectPattern(SI, A, B);
6226 if (SPR.Flavor != SPF_UNKNOWN)
  /src/external/gpl3/binutils/dist/opcodes/
mep-opc.c 785 /* sw $rnl,$udisp7a4($spr) */
788 { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } },
791 /* lw $rnl,$udisp7a4($spr) */
794 { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } },
983 /* add3 $rn,$spr,$uimm7a4 */
986 { { MNEM, ' ', OP (RN), ',', OP (SPR), ',', OP (UIMM7A4), 0 } },
  /src/external/gpl3/binutils.old/dist/opcodes/
mep-opc.c 785 /* sw $rnl,$udisp7a4($spr) */
788 { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } },
791 /* lw $rnl,$udisp7a4($spr) */
794 { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } },
983 /* add3 $rn,$spr,$uimm7a4 */
986 { { MNEM, ' ', OP (RN), ',', OP (SPR), ',', OP (UIMM7A4), 0 } },
  /src/external/gpl3/gdb.old/dist/opcodes/
mep-opc.c 785 /* sw $rnl,$udisp7a4($spr) */
788 { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } },
791 /* lw $rnl,$udisp7a4($spr) */
794 { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } },
983 /* add3 $rn,$spr,$uimm7a4 */
986 { { MNEM, ' ', OP (RN), ',', OP (SPR), ',', OP (UIMM7A4), 0 } },
  /src/external/gpl3/gdb/dist/opcodes/
mep-opc.c 785 /* sw $rnl,$udisp7a4($spr) */
788 { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } },
791 /* lw $rnl,$udisp7a4($spr) */
794 { { MNEM, ' ', OP (RNL), ',', OP (UDISP7A4), '(', OP (SPR), ')', 0 } },
983 /* add3 $rn,$spr,$uimm7a4 */
986 { { MNEM, ' ', OP (RN), ',', OP (SPR), ',', OP (UIMM7A4), 0 } },

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