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    Searched refs:TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/arm/nvidia/
tegra_ahcisatareg.h	121 #define TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 __BITS(7,0)
tegra_ahcisata.c	313 __SHIFTIN(0x23, TEGRA_T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1));

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