1 /* $NetBSD: tlb.h,v 1.9 2026/06/17 15:08:54 rkujawa Exp $ */ 2 3 /* 4 * Copyright 2001 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed for the NetBSD Project by 20 * Wasabi Systems, Inc. 21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 22 * or promote products derived from this software without specific prior 23 * written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 #ifndef _IBM4XX_TLB_H_ 39 #define _IBM4XX_TLB_H_ 40 41 #ifdef _KERNEL_OPT 42 #include "opt_ppcarch.h" 43 #endif 44 45 #define NTLB 64 46 47 /* TLBHI entries */ 48 #define TLB_EPN_MASK 0xfffff000 /* It's 0xfffffc00, but as we use 4K pages we don't need two lower bits */ 49 #define TLB_EPN_SHFT 12 50 #define TLB_SIZE_MASK 0x00000380 51 #define TLB_SIZE_SHFT 7 52 #define TLB_VALID 0x00000040 53 #define TLB_ENDIAN 0x00000020 54 #define TLB_U0 0x00000010 55 56 #define TLB_SIZE_1K 0 57 #define TLB_SIZE_4K 1 58 #define TLB_SIZE_16K 2 59 #define TLB_SIZE_64K 3 60 #define TLB_SIZE_256K 4 61 #define TLB_SIZE_1M 5 62 #define TLB_SIZE_4M 6 63 #define TLB_SIZE_16M 7 64 65 #define TLB_PG_1K (TLB_SIZE_1K << TLB_SIZE_SHFT) 66 #define TLB_PG_4K (TLB_SIZE_4K << TLB_SIZE_SHFT) 67 #define TLB_PG_16K (TLB_SIZE_16K << TLB_SIZE_SHFT) 68 #define TLB_PG_64K (TLB_SIZE_64K << TLB_SIZE_SHFT) 69 #define TLB_PG_256K (TLB_SIZE_256K << TLB_SIZE_SHFT) 70 #define TLB_PG_1M (TLB_SIZE_1M << TLB_SIZE_SHFT) 71 #define TLB_PG_4M (TLB_SIZE_4M << TLB_SIZE_SHFT) 72 #define TLB_PG_16M (TLB_SIZE_16M << TLB_SIZE_SHFT) 73 74 /* TLBLO entries */ 75 #define TLB_RPN_MASK 0xfffffc00 /* Real Page Number mask */ 76 #define TLB_EX 0x00000200 /* EXecute enable */ 77 #define TLB_WR 0x00000100 /* WRite enable */ 78 #define TLB_ZSEL_MASK 0x000000f0 /* Zone SELect mask */ 79 #define TLB_ZSEL_SHFT 4 80 #define TLB_W 0x00000008 /* Write-through */ 81 #define TLB_I 0x00000004 /* Inhibit caching */ 82 #define TLB_M 0x00000002 /* Memory coherent */ 83 #define TLB_G 0x00000001 /* Guarded */ 84 85 #define TLB_ZONE(z) (((z) << TLB_ZSEL_SHFT) & TLB_ZSEL_MASK) 86 87 /* We only need two zones for kernel and user-level processes */ 88 #define TLB_SU_ZONE 0 /* Kernel-only access controlled permission bits in TLB */ 89 #define TLB_U_ZONE 1 /* Access always controlled by permission bits in TLB entry */ 90 91 #define TLB_HI(epn,size,flags) (((epn)&TLB_EPN_MASK)|(((size)<<TLB_SIZE_SHFT)&TLB_SIZE_MASK)|(flags)) 92 #define TLB_LO(rpn,zone,flags) (((rpn)&TLB_RPN_MASK)|(((zone)<<TLB_ZSEL_SHFT)&TLB_ZSEL_MASK)|(flags)) 93 94 /* 95 * 440/460 (Book E) TLB entries 96 */ 97 /* Word 0 */ 98 #define TLB44_EPN_MASK 0xfffffc00 99 #define TLB44_V 0x00000200 /* Valid */ 100 #define TLB44_TS 0x00000100 /* Translation Space */ 101 #define TLB44_SIZE_MASK 0x000000f0 102 #define TLB44_SIZE_SHFT 4 103 /* page size encodings 1K to 16M are identical to the 40x TLB_SIZE_* values */ 104 #define TLB44_SIZE_256M 9 105 #define TLB44_SIZE_1G 10 106 /* Word 1 */ 107 #define TLB44_RPN_MASK 0xfffffc00 108 #define TLB44_ERPN_MASK 0x0000000f /* phys addr bits 32:35 */ 109 /* Word 2 */ 110 #define TLB44_U0 0x00008000 111 #define TLB44_U1 0x00004000 112 #define TLB44_U2 0x00002000 113 #define TLB44_U3 0x00001000 114 #define TLB44_W 0x00000800 /* Write-through */ 115 #define TLB44_I 0x00000400 /* Inhibit caching */ 116 #define TLB44_M 0x00000200 /* Memory coherent */ 117 #define TLB44_G 0x00000100 /* Guarded */ 118 #define TLB44_E 0x00000080 /* Little endian */ 119 #define TLB44_UX 0x00000020 /* User execute */ 120 #define TLB44_UW 0x00000010 /* User write */ 121 #define TLB44_UR 0x00000008 /* User read */ 122 #define TLB44_SX 0x00000004 /* Supervisor execute */ 123 #define TLB44_SW 0x00000002 /* Supervisor write */ 124 #define TLB44_SR 0x00000001 /* Supervisor read */ 125 126 /* 40x TLBLO WIMG flags (TLB_W..TLB_G, also used as TTE_*) -> word 2 */ 127 #define TLB44_WIMG(flags) (((flags) & 0xf) << 8) 128 129 #ifndef _LOCORE 130 131 typedef struct tlb_s { 132 u_int tlb_hi; 133 u_int tlb_lo; 134 } tlb_t; 135 136 struct pmap; 137 138 void ppc4xx_tlb_enter(int, vaddr_t, u_int); 139 void ppc4xx_tlb_flush(vaddr_t, int); 140 void ppc4xx_tlb_flush_all(void); 141 void ppc4xx_tlb_init(void); 142 int ppc4xx_tlb_new_pid(struct pmap *); 143 void ppc4xx_tlb_reserve(paddr_t, vaddr_t, size_t, int); 144 void *ppc4xx_tlb_mapiodev(paddr_t, psize_t); 145 #ifdef PPC_IBM440 146 /* 36-bit physical address variant for 440/460 I/O above 4GB */ 147 void ppc44x_tlb_reserve(uint64_t, vaddr_t, size_t, int); 148 /* pin a TS=0 identity entry for a 256MB RAM chunk above 256MB */ 149 void ppc44x_tlb_reserve_ts0(paddr_t); 150 /* claim locore-pinned boot TLB slots before the first reserve */ 151 void ppc44x_tlb_boot_reserved(int); 152 /* recover the low-32 PA of a VA mapped via a reserved TLB entry */ 153 bool ppc44x_tlb_reverse(vaddr_t, paddr_t *); 154 #endif 155 156 #ifndef ppc4xx_tlbflags 157 #define ppc4xx_tlbflags(va, pa) (0) 158 #endif 159 160 #endif /* !_LOCORE */ 161 162 #define TLB_PID_INVALID 0xFFFF 163 164 #endif /* _IBM4XX_TLB_H_ */ 165
Indexes created Tue Jul 07 00:25:39 UTC 2026