| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/GISel/ |
| PPCRegisterBankInfo.cpp | 26 PPCRegisterBankInfo::PPCRegisterBankInfo(const TargetRegisterInfo &TRI)
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| PPCRegisterBankInfo.h | 35 PPCRegisterBankInfo(const TargetRegisterInfo &TRI);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| RISCVRegisterBankInfo.cpp | 25 RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo &TRI)
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| RISCVRegisterBankInfo.h | 34 RISCVRegisterBankInfo(const TargetRegisterInfo &TRI);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsOptionRecord.h | 46 const MCRegisterInfo *TRI = Context.getRegisterInfo();
47 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
48 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
49 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
50 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
51 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
52 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
53 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
54 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
55 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID))
[all...] |
| MipsFrameLowering.cpp | 95 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
99 TRI->hasStackRealignment(MF);
104 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
106 return MFI.hasVarSizedObjects() && TRI->hasStackRealignment(MF);
116 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
126 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R));
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| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreMachineFunctionInfo.cpp | 39 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
43 LRSpillSlot = MFI.CreateFixedObject(TRI.getSpillSize(RC), 0, true);
45 LRSpillSlot = MFI.CreateStackObject(TRI.getSpillSize(RC),
46 TRI.getSpillAlign(RC), true);
57 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
60 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true);
70 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
72 unsigned Size = TRI.getSpillSize(RC);
73 Align Alignment = TRI.getSpillAlign(RC)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBank.cpp | 32 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
34 for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
53 assert(getSize() >= TRI.getRegSizeInBits(SubRC) &&
82 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
83 print(dbgs(), /* IsForDebug */ true, TRI);
88 const TargetRegisterInfo *TRI) const {
98 if (!TRI || ContainedRegClasses.empty())
100 assert(ContainedRegClasses.size() == TRI->getNumRegClasses() &
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| LivePhysRegs.h | 49 const TargetRegisterInfo *TRI = nullptr;
58 LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) {
59 LiveRegs.setUniverse(TRI.getNumRegs());
66 void init(const TargetRegisterInfo &TRI) {
67 this->TRI = &TRI;
69 LiveRegs.setUniverse(TRI.getNumRegs());
80 assert(TRI && "LivePhysRegs is not initialized.")
[all...] |
| LiveRegUnits.h | 31 const TargetRegisterInfo *TRI = nullptr;
39 LiveRegUnits(const TargetRegisterInfo &TRI) {
40 init(TRI);
50 const TargetRegisterInfo *TRI) {
63 if (!TRI->isConstantPhysReg(Reg))
73 void init(const TargetRegisterInfo &TRI) {
74 this->TRI = &TRI;
76 Units.resize(TRI.getNumRegUnits());
87 for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 48 if (MF->getSubtarget().getRegisterInfo() != TRI) {
49 TRI = MF->getSubtarget().getRegisterInfo();
50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
55 assert(TRI && "no register info set");
62 CalleeSavedAliases.assign(TRI->getNumRegs(), 0);
64 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
71 RegCosts = TRI->getRegisterCosts(*MF);
82 unsigned NumPSets = TRI->getNumRegPressureSets();
150 TRI->getLargestLegalSuperClass(RC, *MF))
158 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["
[all...] |
| LiveRegMatrix.cpp | 56 TRI = MF.getSubtarget().getRegisterInfo();
60 unsigned NumRegUnits = TRI->getNumRegUnits();
80 static bool foreachUnit(const TargetRegisterInfo *TRI,
84 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
96 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg(), TRI) << " to "
106 << printReg(PhysReg, TRI) << ':');
111 TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) {
112 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg(), TRI)
[all...] |
| AllocationOrder.cpp | 33 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
43 dbgs() << ' ' << printReg(Hints[I], TRI);
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| RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI;
60 CoalescerPair(const TargetRegisterInfo &tri) : TRI(tri) {}
65 const TargetRegisterInfo &tri)
66 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {}
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| RegUsageInfoCollector.cpp | 103 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
128 unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
148 for (const MCPhysReg Reg : TRI->getIntraCallClobberedRegs(&MF))
149 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
155 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
162 for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
182 for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
184 dbgs() << printReg(PReg, TRI) << " ";
198 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
207 const MCPhysReg *CSRegs = TRI.getCalleeSavedRegs(&MF)
[all...] |
| MachineCopyPropagation.cpp | 101 const TargetRegisterInfo &TRI) {
104 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) {
113 void invalidateRegister(MCRegister Reg, const TargetRegisterInfo &TRI) {
119 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) {
131 for (MCRegUnitIterator RUI(InvalidReg, &TRI); RUI.isValid(); ++RUI)
136 void clobberRegister(MCRegister Reg, const TargetRegisterInfo &TRI) {
137 for (MCRegUnitIterator RUI(Reg, &TRI); RUI.isValid(); ++RUI) {
142 markRegsUnavailable(I->second.DefRegs, TRI);
146 markRegsUnavailable({MI->getOperand(0).getReg().asMCReg()}, TRI);
154 void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI) {
[all...] |
| FixupStatepointCallerSaved.cpp | 96 static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) {
97 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
98 return TRI.getSpillSize(*RC);
117 const TargetRegisterInfo &TRI) {
119 int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI);
132 if (It->readsRegister(Reg, &TRI) && !Use)
134 if (It->modifiesRegister(Reg, &TRI)) {
149 if (getRegisterSize(TRI, Reg) != getRegisterSize(TRI, SrcReg))
153 << printReg(Reg, &TRI) << " -> " << printReg(SrcReg, &TRI
[all...] |
| AggressiveAntiDepBreaker.cpp | 125 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI) {
129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
139 << " " << printReg(r, TRI));
149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
158 for (MCRegAliasIterator AI(LI.PhysReg, TRI, true); AI.isValid(); ++AI) {
176 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
204 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
213 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)
250 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
306 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| RegisterBank.h | 65 bool verify(const TargetRegisterInfo &TRI) const;
81 void dump(const TargetRegisterInfo *TRI = nullptr) const;
86 /// TRI is then used to print the name of the register classes that
89 const TargetRegisterInfo *TRI = nullptr) const;
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.h | 27 const TargetRegisterInfo *TRI;
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| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMRegisterBankInfo.h | 33 ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| R600ExpandSpecialInstrs.cpp | 74 const R600RegisterInfo &TRI = TII->getRegisterInfo();
124 const R600RegisterInfo &TRI = TII->getRegisterInfo();
127 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
130 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
154 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
155 (TRI.getEncodingValue(Src1) & 0xff) < 127)
156 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
211 Src0 = TRI.getSubReg(Src0, SubRegIndex);
212 Src1 = TRI.getSubReg(Src1, SubRegIndex)
[all...] |
| SIMachineFunctionInfo.cpp | 199 const SIRegisterInfo &TRI) {
201 ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
207 Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
208 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
214 Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
215 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
221 Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
223 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
229 Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
230 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg
[all...] |
| SIFixSGPRCopies.cpp | 92 const SIRegisterInfo *TRI;
128 const SIRegisterInfo *TRI) {
134 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg())))
142 const SIRegisterInfo &TRI,
149 : TRI.getPhysRegClass(SrcReg);
152 // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg());
156 : TRI.getPhysRegClass(DstReg);
163 const SIRegisterInfo &TRI) {
164 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) &&
165 TRI.hasVectorRegisters(SrcRC)
[all...] |
| AMDGPUMacroFusion.cpp | 45 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
48 return FirstMI->definesRegister(Src2->getReg(), TRI);
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