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Searched refs:UVD_CGC_CTRL (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v5_0.c	`666 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) \| 667 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));`
amdgpu_uvd_v6_0.c	`1321 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) \| 1322 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));`
amdgpu_uvd_v7_0.c	`1606 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) \| 1607 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));`
sid.h	`1633 #define UVD_CGC_CTRL 0x3dc2`
/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_si.c	`5183 tmp = RREG32(UVD_CGC_CTRL); 5195 WREG32(UVD_CGC_CTRL, tmp); 5206 u32 tmp = RREG32(UVD_CGC_CTRL); 5208 WREG32(UVD_CGC_CTRL, tmp); 5468 orig = data = RREG32(UVD_CGC_CTRL); 5471 WREG32(UVD_CGC_CTRL, data); 5480 orig = data = RREG32(UVD_CGC_CTRL); 5483 WREG32(UVD_CGC_CTRL, data);`
cikd.h	`2087 #define UVD_CGC_CTRL 0xF4B0`
sid.h	`1570 #define UVD_CGC_CTRL 0xF4B0`
radeon_cik.c	`6240 orig = data = RREG32(UVD_CGC_CTRL); 6243 WREG32(UVD_CGC_CTRL, data); 6249 orig = data = RREG32(UVD_CGC_CTRL); 6252 WREG32(UVD_CGC_CTRL, data);`

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