1 /* $NetBSD: amdgpu_uvd_v5_0.c,v 1.6 2021/12/19 12:21:29 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian Knig <christian.koenig (at) amd.com> 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd_v5_0.c,v 1.6 2021/12/19 12:21:29 riastradh Exp $"); 29 30 #include <linux/delay.h> 31 #include <linux/firmware.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_uvd.h" 35 #include "vid.h" 36 #include "uvd/uvd_5_0_d.h" 37 #include "uvd/uvd_5_0_sh_mask.h" 38 #include "oss/oss_2_0_d.h" 39 #include "oss/oss_2_0_sh_mask.h" 40 #include "bif/bif_5_0_d.h" 41 #include "vi.h" 42 #include "smu/smu_7_1_2_d.h" 43 #include "smu/smu_7_1_2_sh_mask.h" 44 #include "ivsrcid/ivsrcid_vislands30.h" 45 46 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev); 47 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev); 48 static int uvd_v5_0_start(struct amdgpu_device *adev); 49 static void uvd_v5_0_stop(struct amdgpu_device *adev); 50 static int uvd_v5_0_set_clockgating_state(void *handle, 51 enum amd_clockgating_state state); 52 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 53 bool enable); 54 /** 55 * uvd_v5_0_ring_get_rptr - get read pointer 56 * 57 * @ring: amdgpu_ring pointer 58 * 59 * Returns the current hardware read pointer 60 */ 61 static uint64_t uvd_v5_0_ring_get_rptr(struct amdgpu_ring *ring) 62 { 63 struct amdgpu_device *adev = ring->adev; 64 65 return RREG32(mmUVD_RBC_RB_RPTR); 66 } 67 68 /** 69 * uvd_v5_0_ring_get_wptr - get write pointer 70 * 71 * @ring: amdgpu_ring pointer 72 * 73 * Returns the current hardware write pointer 74 */ 75 static uint64_t uvd_v5_0_ring_get_wptr(struct amdgpu_ring *ring) 76 { 77 struct amdgpu_device *adev = ring->adev; 78 79 return RREG32(mmUVD_RBC_RB_WPTR); 80 } 81 82 /** 83 * uvd_v5_0_ring_set_wptr - set write pointer 84 * 85 * @ring: amdgpu_ring pointer 86 * 87 * Commits the write pointer to the hardware 88 */ 89 static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) 90 { 91 struct amdgpu_device *adev = ring->adev; 92 93 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 94 } 95 96 static int uvd_v5_0_early_init(void *handle) 97 { 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 adev->uvd.num_uvd_inst = 1; 100 101 uvd_v5_0_set_ring_funcs(adev); 102 uvd_v5_0_set_irq_funcs(adev); 103 104 return 0; 105 } 106 107 static int uvd_v5_0_sw_init(void *handle) 108 { 109 struct amdgpu_ring *ring; 110 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 111 int r; 112 113 /* UVD TRAP */ 114 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); 115 if (r) 116 return r; 117 118 r = amdgpu_uvd_sw_init(adev); 119 if (r) 120 return r; 121 122 ring = &adev->uvd.inst->ring; 123 snprintf(ring->name, sizeof(ring->name), "uvd"); 124 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); 125 if (r) 126 return r; 127 128 r = amdgpu_uvd_resume(adev); 129 if (r) 130 return r; 131 132 r = amdgpu_uvd_entity_init(adev); 133 134 return r; 135 } 136 137 static int uvd_v5_0_sw_fini(void *handle) 138 { 139 int r; 140 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 141 142 r = amdgpu_uvd_suspend(adev); 143 if (r) 144 return r; 145 146 return amdgpu_uvd_sw_fini(adev); 147 } 148 149 /** 150 * uvd_v5_0_hw_init - start and test UVD block 151 * 152 * @adev: amdgpu_device pointer 153 * 154 * Initialize the hardware, boot up the VCPU and do some testing 155 */ 156 static int uvd_v5_0_hw_init(void *handle) 157 { 158 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 159 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 160 uint32_t tmp; 161 int r; 162 163 amdgpu_asic_set_uvd_clocks(adev, 10000, 10000); 164 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); 165 uvd_v5_0_enable_mgcg(adev, true); 166 167 r = amdgpu_ring_test_helper(ring); 168 if (r) 169 goto done; 170 171 r = amdgpu_ring_alloc(ring, 10); 172 if (r) { 173 DRM_ERROR("amdgpu: ring failed to lock UVD ring (%d).\n", r); 174 goto done; 175 } 176 177 tmp = PACKET0(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL, 0); 178 amdgpu_ring_write(ring, tmp); 179 amdgpu_ring_write(ring, 0xFFFFF); 180 181 tmp = PACKET0(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL, 0); 182 amdgpu_ring_write(ring, tmp); 183 amdgpu_ring_write(ring, 0xFFFFF); 184 185 tmp = PACKET0(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL, 0); 186 amdgpu_ring_write(ring, tmp); 187 amdgpu_ring_write(ring, 0xFFFFF); 188 189 /* Clear timeout status bits */ 190 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_TIMEOUT_STATUS, 0)); 191 amdgpu_ring_write(ring, 0x8); 192 193 amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CNTL, 0)); 194 amdgpu_ring_write(ring, 3); 195 196 amdgpu_ring_commit(ring); 197 198 done: 199 if (!r) 200 DRM_INFO("UVD initialized successfully.\n"); 201 202 return r; 203 204 } 205 206 /** 207 * uvd_v5_0_hw_fini - stop the hardware block 208 * 209 * @adev: amdgpu_device pointer 210 * 211 * Stop the UVD block, mark ring as not ready any more 212 */ 213 static int uvd_v5_0_hw_fini(void *handle) 214 { 215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 216 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 217 218 if (RREG32(mmUVD_STATUS) != 0) 219 uvd_v5_0_stop(adev); 220 221 ring->sched.ready = false; 222 223 return 0; 224 } 225 226 static int uvd_v5_0_suspend(void *handle) 227 { 228 int r; 229 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 230 231 r = uvd_v5_0_hw_fini(adev); 232 if (r) 233 return r; 234 uvd_v5_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); 235 236 return amdgpu_uvd_suspend(adev); 237 } 238 239 static int uvd_v5_0_resume(void *handle) 240 { 241 int r; 242 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 243 244 r = amdgpu_uvd_resume(adev); 245 if (r) 246 return r; 247 248 return uvd_v5_0_hw_init(adev); 249 } 250 251 /** 252 * uvd_v5_0_mc_resume - memory controller programming 253 * 254 * @adev: amdgpu_device pointer 255 * 256 * Let the UVD memory controller know it's offsets 257 */ 258 static void uvd_v5_0_mc_resume(struct amdgpu_device *adev) 259 { 260 uint64_t offset; 261 uint32_t size; 262 263 /* programm memory controller bits 0-27 */ 264 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 265 lower_32_bits(adev->uvd.inst->gpu_addr)); 266 WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 267 upper_32_bits(adev->uvd.inst->gpu_addr)); 268 269 offset = AMDGPU_UVD_FIRMWARE_OFFSET; 270 size = AMDGPU_UVD_FIRMWARE_SIZE(adev); 271 WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3); 272 WREG32(mmUVD_VCPU_CACHE_SIZE0, size); 273 274 offset += size; 275 size = AMDGPU_UVD_HEAP_SIZE; 276 WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3); 277 WREG32(mmUVD_VCPU_CACHE_SIZE1, size); 278 279 offset += size; 280 size = AMDGPU_UVD_STACK_SIZE + 281 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); 282 WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3); 283 WREG32(mmUVD_VCPU_CACHE_SIZE2, size); 284 285 WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 286 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 287 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); 288 } 289 290 /** 291 * uvd_v5_0_start - start UVD block 292 * 293 * @adev: amdgpu_device pointer 294 * 295 * Setup and start the UVD block 296 */ 297 static int uvd_v5_0_start(struct amdgpu_device *adev) 298 { 299 struct amdgpu_ring *ring = &adev->uvd.inst->ring; 300 uint32_t rb_bufsz, tmp; 301 uint32_t lmi_swap_cntl; 302 uint32_t mp_swap_cntl; 303 int i, j, r; 304 305 /*disable DPG */ 306 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); 307 308 /* disable byte swapping */ 309 lmi_swap_cntl = 0; 310 mp_swap_cntl = 0; 311 312 uvd_v5_0_mc_resume(adev); 313 314 /* disable interupt */ 315 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); 316 317 /* stall UMC and register bus before resetting VCPU */ 318 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 319 mdelay(1); 320 321 /* put LMI, VCPU, RBC etc... into reset */ 322 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK | 323 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK | UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK | 324 UVD_SOFT_RESET__RBC_SOFT_RESET_MASK | UVD_SOFT_RESET__CSM_SOFT_RESET_MASK | 325 UVD_SOFT_RESET__CXW_SOFT_RESET_MASK | UVD_SOFT_RESET__TAP_SOFT_RESET_MASK | 326 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 327 mdelay(5); 328 329 /* take UVD block out of reset */ 330 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 331 mdelay(5); 332 333 /* initialize UVD memory controller */ 334 WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) | 335 (1 << 21) | (1 << 9) | (1 << 20)); 336 337 #ifdef __BIG_ENDIAN 338 /* swap (8 in 32) RB and IB */ 339 lmi_swap_cntl = 0xa; 340 mp_swap_cntl = 0; 341 #endif 342 WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 343 WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl); 344 345 WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040); 346 WREG32(mmUVD_MPC_SET_MUXA1, 0x0); 347 WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040); 348 WREG32(mmUVD_MPC_SET_MUXB1, 0x0); 349 WREG32(mmUVD_MPC_SET_ALU, 0); 350 WREG32(mmUVD_MPC_SET_MUX, 0x88); 351 352 /* take all subblocks out of reset, except VCPU */ 353 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 354 mdelay(5); 355 356 /* enable VCPU clock */ 357 WREG32(mmUVD_VCPU_CNTL, 1 << 9); 358 359 /* enable UMC */ 360 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 361 362 /* boot up the VCPU */ 363 WREG32(mmUVD_SOFT_RESET, 0); 364 mdelay(10); 365 366 for (i = 0; i < 10; ++i) { 367 uint32_t status; 368 for (j = 0; j < 100; ++j) { 369 status = RREG32(mmUVD_STATUS); 370 if (status & 2) 371 break; 372 mdelay(10); 373 } 374 r = 0; 375 if (status & 2) 376 break; 377 378 DRM_ERROR("UVD not responding, trying to reset the VCPU!!!\n"); 379 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 380 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 381 mdelay(10); 382 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 383 mdelay(10); 384 r = -1; 385 } 386 387 if (r) { 388 DRM_ERROR("UVD not responding, giving up!!!\n"); 389 return r; 390 } 391 /* enable master interrupt */ 392 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); 393 394 /* clear the bit 4 of UVD_STATUS */ 395 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); 396 397 rb_bufsz = order_base_2(ring->ring_size); 398 tmp = 0; 399 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 400 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 401 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 402 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0); 403 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 404 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 405 /* force RBC into idle state */ 406 WREG32(mmUVD_RBC_RB_CNTL, tmp); 407 408 /* set the write pointer delay */ 409 WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0); 410 411 /* set the wb address */ 412 WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2)); 413 414 /* programm the RB_BASE for ring buffer */ 415 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 416 lower_32_bits(ring->gpu_addr)); 417 WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 418 upper_32_bits(ring->gpu_addr)); 419 420 /* Initialize the ring buffer's read and write pointers */ 421 WREG32(mmUVD_RBC_RB_RPTR, 0); 422 423 ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); 424 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 425 426 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 427 428 return 0; 429 } 430 431 /** 432 * uvd_v5_0_stop - stop UVD block 433 * 434 * @adev: amdgpu_device pointer 435 * 436 * stop the UVD block 437 */ 438 static void uvd_v5_0_stop(struct amdgpu_device *adev) 439 { 440 /* force RBC into idle state */ 441 WREG32(mmUVD_RBC_RB_CNTL, 0x11010101); 442 443 /* Stall UMC and register bus before resetting VCPU */ 444 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); 445 mdelay(1); 446 447 /* put VCPU into reset */ 448 WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 449 mdelay(5); 450 451 /* disable VCPU clock */ 452 WREG32(mmUVD_VCPU_CNTL, 0x0); 453 454 /* Unstall UMC and register bus */ 455 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); 456 457 WREG32(mmUVD_STATUS, 0); 458 } 459 460 /** 461 * uvd_v5_0_ring_emit_fence - emit an fence & trap command 462 * 463 * @ring: amdgpu_ring pointer 464 * @fence: fence to emit 465 * 466 * Write a fence and a trap command to the ring. 467 */ 468 static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 469 unsigned flags) 470 { 471 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 472 473 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 474 amdgpu_ring_write(ring, seq); 475 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 476 amdgpu_ring_write(ring, addr & 0xffffffff); 477 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 478 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 479 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 480 amdgpu_ring_write(ring, 0); 481 482 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0)); 483 amdgpu_ring_write(ring, 0); 484 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0)); 485 amdgpu_ring_write(ring, 0); 486 amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0)); 487 amdgpu_ring_write(ring, 2); 488 } 489 490 /** 491 * uvd_v5_0_ring_test_ring - register write test 492 * 493 * @ring: amdgpu_ring pointer 494 * 495 * Test if we can successfully write to the context register 496 */ 497 static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring) 498 { 499 struct amdgpu_device *adev = ring->adev; 500 uint32_t tmp = 0; 501 unsigned i; 502 int r; 503 504 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); 505 r = amdgpu_ring_alloc(ring, 3); 506 if (r) 507 return r; 508 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); 509 amdgpu_ring_write(ring, 0xDEADBEEF); 510 amdgpu_ring_commit(ring); 511 for (i = 0; i < adev->usec_timeout; i++) { 512 tmp = RREG32(mmUVD_CONTEXT_ID); 513 if (tmp == 0xDEADBEEF) 514 break; 515 udelay(1); 516 } 517 518 if (i >= adev->usec_timeout) 519 r = -ETIMEDOUT; 520 521 return r; 522 } 523 524 /** 525 * uvd_v5_0_ring_emit_ib - execute indirect buffer 526 * 527 * @ring: amdgpu_ring pointer 528 * @ib: indirect buffer to execute 529 * 530 * Write ring commands to execute the indirect buffer 531 */ 532 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, 533 struct amdgpu_job *job, 534 struct amdgpu_ib *ib, 535 uint32_t flags) 536 { 537 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0)); 538 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 539 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH, 0)); 540 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 541 amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_SIZE, 0)); 542 amdgpu_ring_write(ring, ib->length_dw); 543 } 544 545 static void uvd_v5_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 546 { 547 int i; 548 549 WARN_ON(ring->wptr % 2 || count % 2); 550 551 for (i = 0; i < count / 2; i++) { 552 amdgpu_ring_write(ring, PACKET0(mmUVD_NO_OP, 0)); 553 amdgpu_ring_write(ring, 0); 554 } 555 } 556 557 static bool uvd_v5_0_is_idle(void *handle) 558 { 559 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 560 561 return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); 562 } 563 564 static int uvd_v5_0_wait_for_idle(void *handle) 565 { 566 unsigned i; 567 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 568 569 for (i = 0; i < adev->usec_timeout; i++) { 570 if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) 571 return 0; 572 } 573 return -ETIMEDOUT; 574 } 575 576 static int uvd_v5_0_soft_reset(void *handle) 577 { 578 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 579 580 uvd_v5_0_stop(adev); 581 582 WREG32_P(mmSRBM_SOFT_RESET, SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK, 583 ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); 584 mdelay(5); 585 586 return uvd_v5_0_start(adev); 587 } 588 589 static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 590 struct amdgpu_irq_src *source, 591 unsigned type, 592 enum amdgpu_interrupt_state state) 593 { 594 // TODO 595 return 0; 596 } 597 598 static int uvd_v5_0_process_interrupt(struct amdgpu_device *adev, 599 struct amdgpu_irq_src *source, 600 struct amdgpu_iv_entry *entry) 601 { 602 DRM_DEBUG("IH: UVD TRAP\n"); 603 amdgpu_fence_process(&adev->uvd.inst->ring); 604 return 0; 605 } 606 607 static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable) 608 { 609 uint32_t data1, data3, suvd_flags; 610 611 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 612 data3 = RREG32(mmUVD_CGC_GATE); 613 614 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 615 UVD_SUVD_CGC_GATE__SIT_MASK | 616 UVD_SUVD_CGC_GATE__SMP_MASK | 617 UVD_SUVD_CGC_GATE__SCM_MASK | 618 UVD_SUVD_CGC_GATE__SDB_MASK; 619 620 if (enable) { 621 data3 |= (UVD_CGC_GATE__SYS_MASK | 622 UVD_CGC_GATE__UDEC_MASK | 623 UVD_CGC_GATE__MPEG2_MASK | 624 UVD_CGC_GATE__RBC_MASK | 625 UVD_CGC_GATE__LMI_MC_MASK | 626 UVD_CGC_GATE__IDCT_MASK | 627 UVD_CGC_GATE__MPRD_MASK | 628 UVD_CGC_GATE__MPC_MASK | 629 UVD_CGC_GATE__LBSI_MASK | 630 UVD_CGC_GATE__LRBBM_MASK | 631 UVD_CGC_GATE__UDEC_RE_MASK | 632 UVD_CGC_GATE__UDEC_CM_MASK | 633 UVD_CGC_GATE__UDEC_IT_MASK | 634 UVD_CGC_GATE__UDEC_DB_MASK | 635 UVD_CGC_GATE__UDEC_MP_MASK | 636 UVD_CGC_GATE__WCB_MASK | 637 UVD_CGC_GATE__JPEG_MASK | 638 UVD_CGC_GATE__SCPU_MASK); 639 /* only in pg enabled, we can gate clock to vcpu*/ 640 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 641 data3 |= UVD_CGC_GATE__VCPU_MASK; 642 data3 &= ~UVD_CGC_GATE__REGS_MASK; 643 data1 |= suvd_flags; 644 } else { 645 data3 = 0; 646 data1 = 0; 647 } 648 649 WREG32(mmUVD_SUVD_CGC_GATE, data1); 650 WREG32(mmUVD_CGC_GATE, data3); 651 } 652 653 static void uvd_v5_0_set_sw_clock_gating(struct amdgpu_device *adev) 654 { 655 uint32_t data, data2; 656 657 data = RREG32(mmUVD_CGC_CTRL); 658 data2 = RREG32(mmUVD_SUVD_CGC_CTRL); 659 660 661 data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | 662 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK); 663 664 665 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK | 666 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) | 667 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY)); 668 669 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 670 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 671 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 672 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 673 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 674 UVD_CGC_CTRL__SYS_MODE_MASK | 675 UVD_CGC_CTRL__UDEC_MODE_MASK | 676 UVD_CGC_CTRL__MPEG2_MODE_MASK | 677 UVD_CGC_CTRL__REGS_MODE_MASK | 678 UVD_CGC_CTRL__RBC_MODE_MASK | 679 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 680 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 681 UVD_CGC_CTRL__IDCT_MODE_MASK | 682 UVD_CGC_CTRL__MPRD_MODE_MASK | 683 UVD_CGC_CTRL__MPC_MODE_MASK | 684 UVD_CGC_CTRL__LBSI_MODE_MASK | 685 UVD_CGC_CTRL__LRBBM_MODE_MASK | 686 UVD_CGC_CTRL__WCB_MODE_MASK | 687 UVD_CGC_CTRL__VCPU_MODE_MASK | 688 UVD_CGC_CTRL__JPEG_MODE_MASK | 689 UVD_CGC_CTRL__SCPU_MODE_MASK); 690 data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK | 691 UVD_SUVD_CGC_CTRL__SIT_MODE_MASK | 692 UVD_SUVD_CGC_CTRL__SMP_MODE_MASK | 693 UVD_SUVD_CGC_CTRL__SCM_MODE_MASK | 694 UVD_SUVD_CGC_CTRL__SDB_MODE_MASK); 695 696 WREG32(mmUVD_CGC_CTRL, data); 697 WREG32(mmUVD_SUVD_CGC_CTRL, data2); 698 } 699 700 #if 0 701 static void uvd_v5_0_set_hw_clock_gating(struct amdgpu_device *adev) 702 { 703 uint32_t data, data1, cgc_flags, suvd_flags; 704 705 data = RREG32(mmUVD_CGC_GATE); 706 data1 = RREG32(mmUVD_SUVD_CGC_GATE); 707 708 cgc_flags = UVD_CGC_GATE__SYS_MASK | 709 UVD_CGC_GATE__UDEC_MASK | 710 UVD_CGC_GATE__MPEG2_MASK | 711 UVD_CGC_GATE__RBC_MASK | 712 UVD_CGC_GATE__LMI_MC_MASK | 713 UVD_CGC_GATE__IDCT_MASK | 714 UVD_CGC_GATE__MPRD_MASK | 715 UVD_CGC_GATE__MPC_MASK | 716 UVD_CGC_GATE__LBSI_MASK | 717 UVD_CGC_GATE__LRBBM_MASK | 718 UVD_CGC_GATE__UDEC_RE_MASK | 719 UVD_CGC_GATE__UDEC_CM_MASK | 720 UVD_CGC_GATE__UDEC_IT_MASK | 721 UVD_CGC_GATE__UDEC_DB_MASK | 722 UVD_CGC_GATE__UDEC_MP_MASK | 723 UVD_CGC_GATE__WCB_MASK | 724 UVD_CGC_GATE__VCPU_MASK | 725 UVD_CGC_GATE__SCPU_MASK; 726 727 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | 728 UVD_SUVD_CGC_GATE__SIT_MASK | 729 UVD_SUVD_CGC_GATE__SMP_MASK | 730 UVD_SUVD_CGC_GATE__SCM_MASK | 731 UVD_SUVD_CGC_GATE__SDB_MASK; 732 733 data |= cgc_flags; 734 data1 |= suvd_flags; 735 736 WREG32(mmUVD_CGC_GATE, data); 737 WREG32(mmUVD_SUVD_CGC_GATE, data1); 738 } 739 #endif 740 741 static void uvd_v5_0_enable_mgcg(struct amdgpu_device *adev, 742 bool enable) 743 { 744 u32 orig, data; 745 746 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) { 747 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 748 data |= 0xfff; 749 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 750 751 orig = data = RREG32(mmUVD_CGC_CTRL); 752 data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 753 if (orig != data) 754 WREG32(mmUVD_CGC_CTRL, data); 755 } else { 756 data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL); 757 data &= ~0xfff; 758 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); 759 760 orig = data = RREG32(mmUVD_CGC_CTRL); 761 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 762 if (orig != data) 763 WREG32(mmUVD_CGC_CTRL, data); 764 } 765 } 766 767 static int uvd_v5_0_set_clockgating_state(void *handle, 768 enum amd_clockgating_state state) 769 { 770 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 771 bool enable = (state == AMD_CG_STATE_GATE); 772 773 if (enable) { 774 /* wait for STATUS to clear */ 775 if (uvd_v5_0_wait_for_idle(handle)) 776 return -EBUSY; 777 uvd_v5_0_enable_clock_gating(adev, true); 778 779 /* enable HW gates because UVD is idle */ 780 /* uvd_v5_0_set_hw_clock_gating(adev); */ 781 } else { 782 uvd_v5_0_enable_clock_gating(adev, false); 783 } 784 785 uvd_v5_0_set_sw_clock_gating(adev); 786 return 0; 787 } 788 789 static int uvd_v5_0_set_powergating_state(void *handle, 790 enum amd_powergating_state state) 791 { 792 /* This doesn't actually powergate the UVD block. 793 * That's done in the dpm code via the SMC. This 794 * just re-inits the block as necessary. The actual 795 * gating still happens in the dpm code. We should 796 * revisit this when there is a cleaner line between 797 * the smc and the hw blocks 798 */ 799 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 800 int ret = 0; 801 802 if (state == AMD_PG_STATE_GATE) { 803 uvd_v5_0_stop(adev); 804 } else { 805 ret = uvd_v5_0_start(adev); 806 if (ret) 807 goto out; 808 } 809 810 out: 811 return ret; 812 } 813 814 static void uvd_v5_0_get_clockgating_state(void *handle, u32 *flags) 815 { 816 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 817 int data; 818 819 mutex_lock(&adev->pm.mutex); 820 821 if (RREG32_SMC(ixCURRENT_PG_STATUS) & 822 CURRENT_PG_STATUS__UVD_PG_STATUS_MASK) { 823 DRM_INFO("Cannot get clockgating state when UVD is powergated.\n"); 824 goto out; 825 } 826 827 /* AMD_CG_SUPPORT_UVD_MGCG */ 828 data = RREG32(mmUVD_CGC_CTRL); 829 if (data & UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK) 830 *flags |= AMD_CG_SUPPORT_UVD_MGCG; 831 832 out: 833 mutex_unlock(&adev->pm.mutex); 834 } 835 836 static const struct amd_ip_funcs uvd_v5_0_ip_funcs = { 837 .name = "uvd_v5_0", 838 .early_init = uvd_v5_0_early_init, 839 .late_init = NULL, 840 .sw_init = uvd_v5_0_sw_init, 841 .sw_fini = uvd_v5_0_sw_fini, 842 .hw_init = uvd_v5_0_hw_init, 843 .hw_fini = uvd_v5_0_hw_fini, 844 .suspend = uvd_v5_0_suspend, 845 .resume = uvd_v5_0_resume, 846 .is_idle = uvd_v5_0_is_idle, 847 .wait_for_idle = uvd_v5_0_wait_for_idle, 848 .soft_reset = uvd_v5_0_soft_reset, 849 .set_clockgating_state = uvd_v5_0_set_clockgating_state, 850 .set_powergating_state = uvd_v5_0_set_powergating_state, 851 .get_clockgating_state = uvd_v5_0_get_clockgating_state, 852 }; 853 854 static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { 855 .type = AMDGPU_RING_TYPE_UVD, 856 .align_mask = 0xf, 857 .support_64bit_ptrs = false, 858 .no_user_fence = true, 859 .get_rptr = uvd_v5_0_ring_get_rptr, 860 .get_wptr = uvd_v5_0_ring_get_wptr, 861 .set_wptr = uvd_v5_0_ring_set_wptr, 862 .parse_cs = amdgpu_uvd_ring_parse_cs, 863 .emit_frame_size = 864 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ 865 .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ 866 .emit_ib = uvd_v5_0_ring_emit_ib, 867 .emit_fence = uvd_v5_0_ring_emit_fence, 868 .test_ring = uvd_v5_0_ring_test_ring, 869 .test_ib = amdgpu_uvd_ring_test_ib, 870 .insert_nop = uvd_v5_0_ring_insert_nop, 871 .pad_ib = amdgpu_ring_generic_pad_ib, 872 .begin_use = amdgpu_uvd_ring_begin_use, 873 .end_use = amdgpu_uvd_ring_end_use, 874 }; 875 876 static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) 877 { 878 adev->uvd.inst->ring.funcs = &uvd_v5_0_ring_funcs; 879 } 880 881 static const struct amdgpu_irq_src_funcs uvd_v5_0_irq_funcs = { 882 .set = uvd_v5_0_set_interrupt_state, 883 .process = uvd_v5_0_process_interrupt, 884 }; 885 886 static void uvd_v5_0_set_irq_funcs(struct amdgpu_device *adev) 887 { 888 adev->uvd.inst->irq.num_types = 1; 889 adev->uvd.inst->irq.funcs = &uvd_v5_0_irq_funcs; 890 } 891 892 const struct amdgpu_ip_block_version uvd_v5_0_ip_block = 893 { 894 .type = AMD_IP_BLOCK_TYPE_UVD, 895 .major = 5, 896 .minor = 0, 897 .rev = 0, 898 .funcs = &uvd_v5_0_ip_funcs, 899 }; 900
Indexes created Sat Sep 20 22:09:52 GMT 2025