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    Searched refs:UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK (Results 1 - 12 of 12) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_uvd_v4_2.c 615 tmp &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK | UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
amdgpu_uvd_v5_0.c 662 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
amdgpu_uvd_v6_0.c 1317 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
amdgpu_uvd_v7_0.c 1597 UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h 34 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL
uvd_4_2_sh_mask.h 225 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
uvd_5_0_sh_mask.h 247 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
uvd_6_0_sh_mask.h 249 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
uvd_7_0_sh_mask.h 444 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h 937 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
vcn_2_0_0_sh_mask.h 1956 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL
vcn_2_5_sh_mask.h 2005 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL

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