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Searched refs:UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`467 data \|= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 592 data \|= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 594 data \|= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 653 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 655 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;`
amdgpu_vcn_v2_0.c	`461 data \|= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 563 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 565 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 619 data \|= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 621 data \|= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;`
amdgpu_vcn_v2_5.c	`548 data \|= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 654 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 656 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 713 data \|= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 715 data \|= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`39 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x00000000`
uvd_4_2_sh_mask.h	`224 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0`
uvd_5_0_sh_mask.h	`244 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0`
uvd_6_0_sh_mask.h	`246 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0`
uvd_7_0_sh_mask.h	`420 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`913 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0`
vcn_2_0_0_sh_mask.h	`1931 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0`
vcn_2_5_sh_mask.h	`1981 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0`

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