1 /* $NetBSD: amdgpu_vcn_v1_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vcn_v1_0.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 31 #include "amdgpu.h" 32 #include "amdgpu_vcn.h" 33 #include "amdgpu_pm.h" 34 #include "soc15.h" 35 #include "soc15d.h" 36 #include "soc15_common.h" 37 38 #include "vcn/vcn_1_0_offset.h" 39 #include "vcn/vcn_1_0_sh_mask.h" 40 #include "hdp/hdp_4_0_offset.h" 41 #include "mmhub/mmhub_9_1_offset.h" 42 #include "mmhub/mmhub_9_1_sh_mask.h" 43 44 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h" 45 #include "jpeg_v1_0.h" 46 47 #include <linux/nbsd-namespace.h> 48 49 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0 0x05ab 50 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX 1 51 #define mmUVD_REG_XX_MASK_1_0 0x05ac 52 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1 53 54 static int vcn_v1_0_stop(struct amdgpu_device *adev); 55 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); 56 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); 57 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev); 58 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state); 59 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 60 int inst_idx, struct dpg_pause_state *new_state); 61 62 static void vcn_v1_0_idle_work_handler(struct work_struct *work); 63 64 /** 65 * vcn_v1_0_early_init - set function pointers 66 * 67 * @handle: amdgpu_device pointer 68 * 69 * Set ring and irq function pointers 70 */ 71 static int vcn_v1_0_early_init(void *handle) 72 { 73 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 74 75 adev->vcn.num_vcn_inst = 1; 76 adev->vcn.num_enc_rings = 2; 77 78 vcn_v1_0_set_dec_ring_funcs(adev); 79 vcn_v1_0_set_enc_ring_funcs(adev); 80 vcn_v1_0_set_irq_funcs(adev); 81 82 jpeg_v1_0_early_init(handle); 83 84 return 0; 85 } 86 87 /** 88 * vcn_v1_0_sw_init - sw init for VCN block 89 * 90 * @handle: amdgpu_device pointer 91 * 92 * Load firmware and sw initialization 93 */ 94 static int vcn_v1_0_sw_init(void *handle) 95 { 96 struct amdgpu_ring *ring; 97 int i, r; 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 100 /* VCN DEC TRAP */ 101 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 102 VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq); 103 if (r) 104 return r; 105 106 /* VCN ENC TRAP */ 107 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 108 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE, 109 &adev->vcn.inst->irq); 110 if (r) 111 return r; 112 } 113 114 r = amdgpu_vcn_sw_init(adev); 115 if (r) 116 return r; 117 118 /* Override the work func */ 119 adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler; 120 121 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 122 const struct common_firmware_header *hdr; 123 hdr = (const struct common_firmware_header *)adev->vcn.fw->data; 124 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; 125 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw; 126 adev->firmware.fw_size += 127 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE); 128 DRM_INFO("PSP loading VCN firmware\n"); 129 } 130 131 r = amdgpu_vcn_resume(adev); 132 if (r) 133 return r; 134 135 ring = &adev->vcn.inst->ring_dec; 136 snprintf(ring->name, sizeof(ring->name), "vcn_dec"); 137 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); 138 if (r) 139 return r; 140 141 adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 = 142 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9); 143 adev->vcn.internal.data0 = adev->vcn.inst->external.data0 = 144 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0); 145 adev->vcn.internal.data1 = adev->vcn.inst->external.data1 = 146 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1); 147 adev->vcn.internal.cmd = adev->vcn.inst->external.cmd = 148 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD); 149 adev->vcn.internal.nop = adev->vcn.inst->external.nop = 150 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP); 151 152 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 153 ring = &adev->vcn.inst->ring_enc[i]; 154 snprintf(ring->name, sizeof(ring->name), "vcn_enc%d", i); 155 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0); 156 if (r) 157 return r; 158 } 159 160 adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode; 161 162 r = jpeg_v1_0_sw_init(handle); 163 164 return r; 165 } 166 167 /** 168 * vcn_v1_0_sw_fini - sw fini for VCN block 169 * 170 * @handle: amdgpu_device pointer 171 * 172 * VCN suspend and free up sw allocation 173 */ 174 static int vcn_v1_0_sw_fini(void *handle) 175 { 176 int r; 177 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 178 179 r = amdgpu_vcn_suspend(adev); 180 if (r) 181 return r; 182 183 jpeg_v1_0_sw_fini(handle); 184 185 r = amdgpu_vcn_sw_fini(adev); 186 187 return r; 188 } 189 190 /** 191 * vcn_v1_0_hw_init - start and test VCN block 192 * 193 * @handle: amdgpu_device pointer 194 * 195 * Initialize the hardware, boot up the VCPU and do some testing 196 */ 197 static int vcn_v1_0_hw_init(void *handle) 198 { 199 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 200 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 201 int i, r; 202 203 r = amdgpu_ring_test_helper(ring); 204 if (r) 205 goto done; 206 207 for (i = 0; i < adev->vcn.num_enc_rings; ++i) { 208 ring = &adev->vcn.inst->ring_enc[i]; 209 r = amdgpu_ring_test_helper(ring); 210 if (r) 211 goto done; 212 } 213 214 ring = &adev->jpeg.inst->ring_dec; 215 r = amdgpu_ring_test_helper(ring); 216 if (r) 217 goto done; 218 219 done: 220 if (!r) 221 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n", 222 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode"); 223 224 return r; 225 } 226 227 /** 228 * vcn_v1_0_hw_fini - stop the hardware block 229 * 230 * @handle: amdgpu_device pointer 231 * 232 * Stop the VCN block, mark ring as not ready any more 233 */ 234 static int vcn_v1_0_hw_fini(void *handle) 235 { 236 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 237 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 238 239 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) || 240 RREG32_SOC15(VCN, 0, mmUVD_STATUS)) 241 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE); 242 243 ring->sched.ready = false; 244 245 return 0; 246 } 247 248 /** 249 * vcn_v1_0_suspend - suspend VCN block 250 * 251 * @handle: amdgpu_device pointer 252 * 253 * HW fini and suspend VCN block 254 */ 255 static int vcn_v1_0_suspend(void *handle) 256 { 257 int r; 258 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 259 260 r = vcn_v1_0_hw_fini(adev); 261 if (r) 262 return r; 263 264 r = amdgpu_vcn_suspend(adev); 265 266 return r; 267 } 268 269 /** 270 * vcn_v1_0_resume - resume VCN block 271 * 272 * @handle: amdgpu_device pointer 273 * 274 * Resume firmware and hw init VCN block 275 */ 276 static int vcn_v1_0_resume(void *handle) 277 { 278 int r; 279 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 280 281 r = amdgpu_vcn_resume(adev); 282 if (r) 283 return r; 284 285 r = vcn_v1_0_hw_init(adev); 286 287 return r; 288 } 289 290 /** 291 * vcn_v1_0_mc_resume_spg_mode - memory controller programming 292 * 293 * @adev: amdgpu_device pointer 294 * 295 * Let the VCN memory controller know it's offsets 296 */ 297 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev) 298 { 299 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 300 uint32_t offset; 301 302 /* cache window 0: fw */ 303 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 304 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 305 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); 306 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 307 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi)); 308 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0); 309 offset = 0; 310 } else { 311 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 312 lower_32_bits(adev->vcn.inst->gpu_addr)); 313 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 314 upper_32_bits(adev->vcn.inst->gpu_addr)); 315 offset = size; 316 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 317 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); 318 } 319 320 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); 321 322 /* cache window 1: stack */ 323 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 324 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); 325 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 326 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); 327 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0); 328 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); 329 330 /* cache window 2: context */ 331 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 332 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 333 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 334 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); 335 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0); 336 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); 337 338 WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 339 adev->gfx.config.gb_addr_config); 340 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 341 adev->gfx.config.gb_addr_config); 342 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 343 adev->gfx.config.gb_addr_config); 344 WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 345 adev->gfx.config.gb_addr_config); 346 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 347 adev->gfx.config.gb_addr_config); 348 WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 349 adev->gfx.config.gb_addr_config); 350 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 351 adev->gfx.config.gb_addr_config); 352 WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 353 adev->gfx.config.gb_addr_config); 354 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 355 adev->gfx.config.gb_addr_config); 356 WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 357 adev->gfx.config.gb_addr_config); 358 WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, 359 adev->gfx.config.gb_addr_config); 360 WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, 361 adev->gfx.config.gb_addr_config); 362 } 363 364 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev) 365 { 366 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4); 367 uint32_t offset; 368 369 /* cache window 0: fw */ 370 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 371 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 372 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 373 0xFFFFFFFF, 0); 374 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 375 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 376 0xFFFFFFFF, 0); 377 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0, 378 0xFFFFFFFF, 0); 379 offset = 0; 380 } else { 381 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, 382 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 383 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, 384 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); 385 offset = size; 386 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 387 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); 388 } 389 390 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); 391 392 /* cache window 1: stack */ 393 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, 394 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 395 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, 396 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); 397 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0, 398 0xFFFFFFFF, 0); 399 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE, 400 0xFFFFFFFF, 0); 401 402 /* cache window 2: context */ 403 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, 404 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 405 0xFFFFFFFF, 0); 406 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, 407 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 408 0xFFFFFFFF, 0); 409 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0); 410 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE, 411 0xFFFFFFFF, 0); 412 413 /* VCN global tiling registers */ 414 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_ADDR_CONFIG, 415 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 416 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG, 417 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 418 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG, 419 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 420 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG, 421 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 422 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG, 423 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 424 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG, 425 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 426 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG, 427 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 428 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG, 429 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 430 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG, 431 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 432 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG, 433 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0); 434 } 435 436 /** 437 * vcn_v1_0_disable_clock_gating - disable VCN clock gating 438 * 439 * @adev: amdgpu_device pointer 440 * @sw: enable SW clock gating 441 * 442 * Disable clock gating for VCN block 443 */ 444 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev) 445 { 446 uint32_t data; 447 448 /* JPEG disable CGC */ 449 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 450 451 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 452 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 453 else 454 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK; 455 456 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 457 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 458 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 459 460 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 461 data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 462 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 463 464 /* UVD disable CGC */ 465 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 466 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 467 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 468 else 469 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK; 470 471 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 472 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 473 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 474 475 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); 476 data &= ~(UVD_CGC_GATE__SYS_MASK 477 | UVD_CGC_GATE__UDEC_MASK 478 | UVD_CGC_GATE__MPEG2_MASK 479 | UVD_CGC_GATE__REGS_MASK 480 | UVD_CGC_GATE__RBC_MASK 481 | UVD_CGC_GATE__LMI_MC_MASK 482 | UVD_CGC_GATE__LMI_UMC_MASK 483 | UVD_CGC_GATE__IDCT_MASK 484 | UVD_CGC_GATE__MPRD_MASK 485 | UVD_CGC_GATE__MPC_MASK 486 | UVD_CGC_GATE__LBSI_MASK 487 | UVD_CGC_GATE__LRBBM_MASK 488 | UVD_CGC_GATE__UDEC_RE_MASK 489 | UVD_CGC_GATE__UDEC_CM_MASK 490 | UVD_CGC_GATE__UDEC_IT_MASK 491 | UVD_CGC_GATE__UDEC_DB_MASK 492 | UVD_CGC_GATE__UDEC_MP_MASK 493 | UVD_CGC_GATE__WCB_MASK 494 | UVD_CGC_GATE__VCPU_MASK 495 | UVD_CGC_GATE__SCPU_MASK); 496 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); 497 498 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 499 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK 500 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 501 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 502 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 503 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 504 | UVD_CGC_CTRL__SYS_MODE_MASK 505 | UVD_CGC_CTRL__UDEC_MODE_MASK 506 | UVD_CGC_CTRL__MPEG2_MODE_MASK 507 | UVD_CGC_CTRL__REGS_MODE_MASK 508 | UVD_CGC_CTRL__RBC_MODE_MASK 509 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 510 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 511 | UVD_CGC_CTRL__IDCT_MODE_MASK 512 | UVD_CGC_CTRL__MPRD_MODE_MASK 513 | UVD_CGC_CTRL__MPC_MODE_MASK 514 | UVD_CGC_CTRL__LBSI_MODE_MASK 515 | UVD_CGC_CTRL__LRBBM_MODE_MASK 516 | UVD_CGC_CTRL__WCB_MODE_MASK 517 | UVD_CGC_CTRL__VCPU_MODE_MASK 518 | UVD_CGC_CTRL__SCPU_MODE_MASK); 519 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 520 521 /* turn on */ 522 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE); 523 data |= (UVD_SUVD_CGC_GATE__SRE_MASK 524 | UVD_SUVD_CGC_GATE__SIT_MASK 525 | UVD_SUVD_CGC_GATE__SMP_MASK 526 | UVD_SUVD_CGC_GATE__SCM_MASK 527 | UVD_SUVD_CGC_GATE__SDB_MASK 528 | UVD_SUVD_CGC_GATE__SRE_H264_MASK 529 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 530 | UVD_SUVD_CGC_GATE__SIT_H264_MASK 531 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 532 | UVD_SUVD_CGC_GATE__SCM_H264_MASK 533 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 534 | UVD_SUVD_CGC_GATE__SDB_H264_MASK 535 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 536 | UVD_SUVD_CGC_GATE__SCLR_MASK 537 | UVD_SUVD_CGC_GATE__UVD_SC_MASK 538 | UVD_SUVD_CGC_GATE__ENT_MASK 539 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 540 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 541 | UVD_SUVD_CGC_GATE__SITE_MASK 542 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK 543 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK 544 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 545 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK 546 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK); 547 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data); 548 549 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 550 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 551 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 552 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 553 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 554 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 555 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 556 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 557 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 558 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 559 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 560 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 561 } 562 563 /** 564 * vcn_v1_0_enable_clock_gating - enable VCN clock gating 565 * 566 * @adev: amdgpu_device pointer 567 * @sw: enable SW clock gating 568 * 569 * Enable clock gating for VCN block 570 */ 571 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev) 572 { 573 uint32_t data = 0; 574 575 /* enable JPEG CGC */ 576 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL); 577 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 578 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 579 else 580 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 581 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 582 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 583 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); 584 585 data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE); 586 data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK); 587 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); 588 589 /* enable UVD CGC */ 590 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 591 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 592 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 593 else 594 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 595 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 596 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 597 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 598 599 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); 600 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK 601 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK 602 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK 603 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK 604 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK 605 | UVD_CGC_CTRL__SYS_MODE_MASK 606 | UVD_CGC_CTRL__UDEC_MODE_MASK 607 | UVD_CGC_CTRL__MPEG2_MODE_MASK 608 | UVD_CGC_CTRL__REGS_MODE_MASK 609 | UVD_CGC_CTRL__RBC_MODE_MASK 610 | UVD_CGC_CTRL__LMI_MC_MODE_MASK 611 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK 612 | UVD_CGC_CTRL__IDCT_MODE_MASK 613 | UVD_CGC_CTRL__MPRD_MODE_MASK 614 | UVD_CGC_CTRL__MPC_MODE_MASK 615 | UVD_CGC_CTRL__LBSI_MODE_MASK 616 | UVD_CGC_CTRL__LRBBM_MODE_MASK 617 | UVD_CGC_CTRL__WCB_MODE_MASK 618 | UVD_CGC_CTRL__VCPU_MODE_MASK 619 | UVD_CGC_CTRL__SCPU_MODE_MASK); 620 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); 621 622 data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL); 623 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 624 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 625 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 626 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 627 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 628 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 629 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 630 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 631 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK 632 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK); 633 WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data); 634 } 635 636 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel) 637 { 638 uint32_t reg_data = 0; 639 640 /* disable JPEG CGC */ 641 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 642 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 643 else 644 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 645 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 646 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 647 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 648 649 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 650 651 /* enable sw clock gating control */ 652 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG) 653 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 654 else 655 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT; 656 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT; 657 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT; 658 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK | 659 UVD_CGC_CTRL__UDEC_CM_MODE_MASK | 660 UVD_CGC_CTRL__UDEC_IT_MODE_MASK | 661 UVD_CGC_CTRL__UDEC_DB_MODE_MASK | 662 UVD_CGC_CTRL__UDEC_MP_MODE_MASK | 663 UVD_CGC_CTRL__SYS_MODE_MASK | 664 UVD_CGC_CTRL__UDEC_MODE_MASK | 665 UVD_CGC_CTRL__MPEG2_MODE_MASK | 666 UVD_CGC_CTRL__REGS_MODE_MASK | 667 UVD_CGC_CTRL__RBC_MODE_MASK | 668 UVD_CGC_CTRL__LMI_MC_MODE_MASK | 669 UVD_CGC_CTRL__LMI_UMC_MODE_MASK | 670 UVD_CGC_CTRL__IDCT_MODE_MASK | 671 UVD_CGC_CTRL__MPRD_MODE_MASK | 672 UVD_CGC_CTRL__MPC_MODE_MASK | 673 UVD_CGC_CTRL__LBSI_MODE_MASK | 674 UVD_CGC_CTRL__LRBBM_MODE_MASK | 675 UVD_CGC_CTRL__WCB_MODE_MASK | 676 UVD_CGC_CTRL__VCPU_MODE_MASK | 677 UVD_CGC_CTRL__SCPU_MODE_MASK); 678 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); 679 680 /* turn off clock gating */ 681 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel); 682 683 /* turn on SUVD clock gating */ 684 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel); 685 686 /* turn on sw mode in UVD_SUVD_CGC_CTRL */ 687 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel); 688 } 689 690 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev) 691 { 692 uint32_t data = 0; 693 int ret __unused; 694 695 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 696 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 697 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 698 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 699 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 700 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 701 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 702 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 703 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 704 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 705 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 706 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 707 708 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 709 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF, ret); 710 } else { 711 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 712 | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 713 | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 714 | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 715 | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 716 | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 717 | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 718 | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 719 | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 720 | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 721 | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 722 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 723 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFFFFF, ret); 724 } 725 726 /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */ 727 728 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 729 data &= ~0x103; 730 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) 731 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; 732 733 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 734 } 735 736 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev) 737 { 738 uint32_t data = 0; 739 int ret __unused; 740 741 if (adev->pg_flags & AMD_PG_SUPPORT_VCN) { 742 /* Before power off, this indicator has to be turned on */ 743 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); 744 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK; 745 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF; 746 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); 747 748 749 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 750 | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 751 | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 752 | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 753 | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 754 | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 755 | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 756 | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 757 | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 758 | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 759 | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT); 760 761 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data); 762 763 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 764 | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 765 | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 766 | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 767 | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 768 | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 769 | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 770 | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 771 | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 772 | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 773 | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT); 774 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF, ret); 775 } 776 } 777 778 /** 779 * vcn_v1_0_start - start VCN block 780 * 781 * @adev: amdgpu_device pointer 782 * 783 * Setup and start the VCN block 784 */ 785 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev) 786 { 787 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 788 uint32_t rb_bufsz, tmp; 789 uint32_t lmi_swap_cntl; 790 int i, j, r; 791 792 /* disable byte swapping */ 793 lmi_swap_cntl = 0; 794 795 vcn_1_0_disable_static_power_gating(adev); 796 797 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; 798 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 799 800 /* disable clock gating */ 801 vcn_v1_0_disable_clock_gating(adev); 802 803 /* disable interupt */ 804 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, 805 ~UVD_MASTINT_EN__VCPU_EN_MASK); 806 807 /* initialize VCN memory controller */ 808 tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL); 809 WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp | 810 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 811 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 812 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 813 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK); 814 815 #ifdef __BIG_ENDIAN 816 /* swap (8 in 32) RB and IB */ 817 lmi_swap_cntl = 0xa; 818 #endif 819 WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl); 820 821 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); 822 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK; 823 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT; 824 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); 825 826 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0, 827 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 828 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 829 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 830 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 831 832 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0, 833 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 834 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 835 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 836 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT))); 837 838 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, 839 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 840 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 841 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT))); 842 843 vcn_v1_0_mc_resume_spg_mode(adev); 844 845 WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10); 846 WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0, 847 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3); 848 849 /* enable VCPU clock */ 850 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK); 851 852 /* boot up the VCPU */ 853 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 854 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 855 856 /* enable UMC */ 857 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0, 858 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK); 859 860 tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET); 861 tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK; 862 tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK; 863 WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp); 864 865 for (i = 0; i < 10; ++i) { 866 uint32_t status; 867 868 for (j = 0; j < 100; ++j) { 869 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); 870 if (status & UVD_STATUS__IDLE) 871 break; 872 mdelay(10); 873 } 874 r = 0; 875 if (status & UVD_STATUS__IDLE) 876 break; 877 878 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n"); 879 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 880 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 881 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 882 mdelay(10); 883 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0, 884 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 885 mdelay(10); 886 r = -1; 887 } 888 889 if (r) { 890 DRM_ERROR("VCN decode not responding, giving up!!!\n"); 891 return r; 892 } 893 /* enable master interrupt */ 894 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 895 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK); 896 897 /* enable system interrupt for JRBC, TODO: move to set interrupt*/ 898 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), 899 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 900 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK); 901 902 /* clear the busy bit of UVD_STATUS */ 903 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; 904 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); 905 906 /* force RBC into idle state */ 907 rb_bufsz = order_base_2(ring->ring_size); 908 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 909 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 910 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 911 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 912 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 913 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 914 915 /* set the write pointer delay */ 916 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 917 918 /* set the wb address */ 919 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 920 (upper_32_bits(ring->gpu_addr) >> 2)); 921 922 /* programm the RB_BASE for ring buffer */ 923 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 924 lower_32_bits(ring->gpu_addr)); 925 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 926 upper_32_bits(ring->gpu_addr)); 927 928 /* Initialize the ring buffer's read and write pointers */ 929 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 930 931 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 932 933 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 934 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 935 lower_32_bits(ring->wptr)); 936 937 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 938 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 939 940 ring = &adev->vcn.inst->ring_enc[0]; 941 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 942 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 943 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 944 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 945 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 946 947 ring = &adev->vcn.inst->ring_enc[1]; 948 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 949 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 950 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 951 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 952 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 953 954 jpeg_v1_0_start(adev, 0); 955 956 return 0; 957 } 958 959 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev) 960 { 961 struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; 962 uint32_t rb_bufsz, tmp; 963 uint32_t lmi_swap_cntl; 964 965 /* disable byte swapping */ 966 lmi_swap_cntl = 0; 967 968 vcn_1_0_enable_static_power_gating(adev); 969 970 /* enable dynamic power gating mode */ 971 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 972 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK; 973 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; 974 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); 975 976 /* enable clock gating */ 977 vcn_v1_0_clock_gating_dpg_mode(adev, 0); 978 979 /* enable VCPU clock */ 980 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT); 981 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK; 982 tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK; 983 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0); 984 985 /* disable interupt */ 986 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 987 0, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 988 989 /* initialize VCN memory controller */ 990 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 991 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 992 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 993 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 994 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 995 UVD_LMI_CTRL__REQ_MODE_MASK | 996 UVD_LMI_CTRL__CRC_RESET_MASK | 997 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 998 0x00100000L, 0xFFFFFFFF, 0); 999 1000 #ifdef __BIG_ENDIAN 1001 /* swap (8 in 32) RB and IB */ 1002 lmi_swap_cntl = 0xa; 1003 #endif 1004 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0); 1005 1006 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_CNTL, 1007 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0); 1008 1009 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXA0, 1010 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) | 1011 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) | 1012 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) | 1013 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0); 1014 1015 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUXB0, 1016 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) | 1017 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) | 1018 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) | 1019 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0); 1020 1021 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MPC_SET_MUX, 1022 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) | 1023 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) | 1024 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0); 1025 1026 vcn_v1_0_mc_resume_dpg_mode(adev); 1027 1028 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0); 1029 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0); 1030 1031 /* boot up the VCPU */ 1032 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0); 1033 1034 /* enable UMC */ 1035 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL2, 1036 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 1037 0xFFFFFFFF, 0); 1038 1039 /* enable master interrupt */ 1040 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_MASTINT_EN, 1041 UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0); 1042 1043 vcn_v1_0_clock_gating_dpg_mode(adev, 1); 1044 /* setup mmUVD_LMI_CTRL */ 1045 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_LMI_CTRL, 1046 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) | 1047 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK | 1048 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK | 1049 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK | 1050 UVD_LMI_CTRL__REQ_MODE_MASK | 1051 UVD_LMI_CTRL__CRC_RESET_MASK | 1052 UVD_LMI_CTRL__MASK_MC_URGENT_MASK | 1053 0x00100000L, 0xFFFFFFFF, 1); 1054 1055 tmp = adev->gfx.config.gb_addr_config; 1056 /* setup VCN global tiling registers */ 1057 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1058 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1); 1059 1060 /* enable System Interrupt for JRBC */ 1061 WREG32_SOC15_DPG_MODE(UVD, 0, mmUVD_SYS_INT_EN, 1062 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1); 1063 1064 /* force RBC into idle state */ 1065 rb_bufsz = order_base_2(ring->ring_size); 1066 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); 1067 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1); 1068 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1); 1069 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1); 1070 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1); 1071 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp); 1072 1073 /* set the write pointer delay */ 1074 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0); 1075 1076 /* set the wb address */ 1077 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR, 1078 (upper_32_bits(ring->gpu_addr) >> 2)); 1079 1080 /* programm the RB_BASE for ring buffer */ 1081 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 1082 lower_32_bits(ring->gpu_addr)); 1083 WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 1084 upper_32_bits(ring->gpu_addr)); 1085 1086 /* Initialize the ring buffer's read and write pointers */ 1087 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0); 1088 1089 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); 1090 1091 ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1092 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1093 lower_32_bits(ring->wptr)); 1094 1095 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0, 1096 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); 1097 1098 jpeg_v1_0_start(adev, 1); 1099 1100 return 0; 1101 } 1102 1103 static int vcn_v1_0_start(struct amdgpu_device *adev) 1104 { 1105 int r; 1106 1107 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1108 r = vcn_v1_0_start_dpg_mode(adev); 1109 else 1110 r = vcn_v1_0_start_spg_mode(adev); 1111 return r; 1112 } 1113 1114 /** 1115 * vcn_v1_0_stop - stop VCN block 1116 * 1117 * @adev: amdgpu_device pointer 1118 * 1119 * stop the VCN block 1120 */ 1121 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev) 1122 { 1123 int ret_code __unused, tmp; 1124 1125 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7, ret_code); 1126 1127 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK | 1128 UVD_LMI_STATUS__READ_CLEAN_MASK | 1129 UVD_LMI_STATUS__WRITE_CLEAN_MASK | 1130 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK; 1131 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1132 1133 /* put VCPU into reset */ 1134 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1135 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, 1136 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); 1137 1138 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK | 1139 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK; 1140 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp, ret_code); 1141 1142 /* disable VCPU clock */ 1143 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0, 1144 ~UVD_VCPU_CNTL__CLK_EN_MASK); 1145 1146 /* reset LMI UMC/LMI */ 1147 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1148 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK, 1149 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK); 1150 1151 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 1152 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK, 1153 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK); 1154 1155 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); 1156 1157 vcn_v1_0_enable_clock_gating(adev); 1158 vcn_1_0_enable_static_power_gating(adev); 1159 return 0; 1160 } 1161 1162 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev) 1163 { 1164 int ret_code __unused = 0; 1165 uint32_t tmp; 1166 1167 /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */ 1168 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1169 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1170 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1171 1172 /* wait for read ptr to be equal to write ptr */ 1173 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1174 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1175 1176 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1177 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF, ret_code); 1178 1179 tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); 1180 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1181 1182 tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; 1183 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF, ret_code); 1184 1185 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1186 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1187 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1188 1189 /* disable dynamic power gating mode */ 1190 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0, 1191 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK); 1192 1193 return 0; 1194 } 1195 1196 static int vcn_v1_0_stop(struct amdgpu_device *adev) 1197 { 1198 int r; 1199 1200 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1201 r = vcn_v1_0_stop_dpg_mode(adev); 1202 else 1203 r = vcn_v1_0_stop_spg_mode(adev); 1204 1205 return r; 1206 } 1207 1208 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev, 1209 int inst_idx, struct dpg_pause_state *new_state) 1210 { 1211 int ret_code; 1212 uint32_t reg_data = 0; 1213 uint32_t reg_data2 = 0; 1214 struct amdgpu_ring *ring; 1215 1216 /* pause/unpause if state is changed */ 1217 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { 1218 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1219 adev->vcn.inst[inst_idx].pause_state.fw_based, 1220 adev->vcn.inst[inst_idx].pause_state.jpeg, 1221 new_state->fw_based, new_state->jpeg); 1222 1223 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1224 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 1225 1226 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 1227 ret_code = 0; 1228 1229 if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK)) 1230 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1231 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1232 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1233 1234 if (!ret_code) { 1235 /* pause DPG non-jpeg */ 1236 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1237 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1238 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1239 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 1240 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code); 1241 1242 /* Restore */ 1243 ring = &adev->vcn.inst->ring_enc[0]; 1244 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); 1245 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); 1246 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); 1247 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); 1248 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); 1249 1250 ring = &adev->vcn.inst->ring_enc[1]; 1251 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr); 1252 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); 1253 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4); 1254 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); 1255 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); 1256 1257 ring = &adev->vcn.inst->ring_dec; 1258 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1259 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1260 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1261 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1262 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1263 } 1264 } else { 1265 /* unpause dpg non-jpeg, no need to wait */ 1266 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 1267 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1268 } 1269 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; 1270 } 1271 1272 /* pause/unpause if state is changed */ 1273 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { 1274 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d", 1275 adev->vcn.inst[inst_idx].pause_state.fw_based, 1276 adev->vcn.inst[inst_idx].pause_state.jpeg, 1277 new_state->fw_based, new_state->jpeg); 1278 1279 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) & 1280 (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK); 1281 1282 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) { 1283 ret_code = 0; 1284 1285 if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)) 1286 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1287 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF, 1288 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1289 1290 if (!ret_code) { 1291 /* Make sure JPRG Snoop is disabled before sending the pause */ 1292 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); 1293 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK; 1294 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2); 1295 1296 /* pause DPG jpeg */ 1297 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1298 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1299 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, 1300 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, 1301 UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK, ret_code); 1302 1303 /* Restore */ 1304 ring = &adev->jpeg.inst->ring_dec; 1305 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); 1306 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1307 UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | 1308 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1309 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, 1310 lower_32_bits(ring->gpu_addr)); 1311 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, 1312 upper_32_bits(ring->gpu_addr)); 1313 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); 1314 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); 1315 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 1316 UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); 1317 1318 ring = &adev->vcn.inst->ring_dec; 1319 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, 1320 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); 1321 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1322 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, 1323 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); 1324 } 1325 } else { 1326 /* unpause dpg jpeg, no need to wait */ 1327 reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK; 1328 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data); 1329 } 1330 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; 1331 } 1332 1333 return 0; 1334 } 1335 1336 static bool vcn_v1_0_is_idle(void *handle) 1337 { 1338 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1339 1340 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); 1341 } 1342 1343 static int vcn_v1_0_wait_for_idle(void *handle) 1344 { 1345 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1346 int ret = 0; 1347 1348 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 1349 UVD_STATUS__IDLE, ret); 1350 1351 return ret; 1352 } 1353 1354 static int vcn_v1_0_set_clockgating_state(void *handle, 1355 enum amd_clockgating_state state) 1356 { 1357 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1358 bool enable = (state == AMD_CG_STATE_GATE); 1359 1360 if (enable) { 1361 /* wait for STATUS to clear */ 1362 if (vcn_v1_0_is_idle(handle)) 1363 return -EBUSY; 1364 vcn_v1_0_enable_clock_gating(adev); 1365 } else { 1366 /* disable HW gating and enable Sw gating */ 1367 vcn_v1_0_disable_clock_gating(adev); 1368 } 1369 return 0; 1370 } 1371 1372 /** 1373 * vcn_v1_0_dec_ring_get_rptr - get read pointer 1374 * 1375 * @ring: amdgpu_ring pointer 1376 * 1377 * Returns the current hardware read pointer 1378 */ 1379 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring) 1380 { 1381 struct amdgpu_device *adev = ring->adev; 1382 1383 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); 1384 } 1385 1386 /** 1387 * vcn_v1_0_dec_ring_get_wptr - get write pointer 1388 * 1389 * @ring: amdgpu_ring pointer 1390 * 1391 * Returns the current hardware write pointer 1392 */ 1393 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring) 1394 { 1395 struct amdgpu_device *adev = ring->adev; 1396 1397 return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR); 1398 } 1399 1400 /** 1401 * vcn_v1_0_dec_ring_set_wptr - set write pointer 1402 * 1403 * @ring: amdgpu_ring pointer 1404 * 1405 * Commits the write pointer to the hardware 1406 */ 1407 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring) 1408 { 1409 struct amdgpu_device *adev = ring->adev; 1410 1411 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) 1412 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 1413 lower_32_bits(ring->wptr) | 0x80000000); 1414 1415 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); 1416 } 1417 1418 /** 1419 * vcn_v1_0_dec_ring_insert_start - insert a start command 1420 * 1421 * @ring: amdgpu_ring pointer 1422 * 1423 * Write a start command to the ring. 1424 */ 1425 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring) 1426 { 1427 struct amdgpu_device *adev = ring->adev; 1428 1429 amdgpu_ring_write(ring, 1430 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1431 amdgpu_ring_write(ring, 0); 1432 amdgpu_ring_write(ring, 1433 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1434 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1); 1435 } 1436 1437 /** 1438 * vcn_v1_0_dec_ring_insert_end - insert a end command 1439 * 1440 * @ring: amdgpu_ring pointer 1441 * 1442 * Write a end command to the ring. 1443 */ 1444 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring) 1445 { 1446 struct amdgpu_device *adev = ring->adev; 1447 1448 amdgpu_ring_write(ring, 1449 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1450 amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1); 1451 } 1452 1453 /** 1454 * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command 1455 * 1456 * @ring: amdgpu_ring pointer 1457 * @fence: fence to emit 1458 * 1459 * Write a fence and a trap command to the ring. 1460 */ 1461 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 1462 unsigned flags) 1463 { 1464 struct amdgpu_device *adev = ring->adev; 1465 1466 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1467 1468 amdgpu_ring_write(ring, 1469 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); 1470 amdgpu_ring_write(ring, seq); 1471 amdgpu_ring_write(ring, 1472 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1473 amdgpu_ring_write(ring, addr & 0xffffffff); 1474 amdgpu_ring_write(ring, 1475 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1476 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff); 1477 amdgpu_ring_write(ring, 1478 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1479 amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1); 1480 1481 amdgpu_ring_write(ring, 1482 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1483 amdgpu_ring_write(ring, 0); 1484 amdgpu_ring_write(ring, 1485 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1486 amdgpu_ring_write(ring, 0); 1487 amdgpu_ring_write(ring, 1488 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1489 amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1); 1490 } 1491 1492 /** 1493 * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer 1494 * 1495 * @ring: amdgpu_ring pointer 1496 * @ib: indirect buffer to execute 1497 * 1498 * Write ring commands to execute the indirect buffer 1499 */ 1500 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring, 1501 struct amdgpu_job *job, 1502 struct amdgpu_ib *ib, 1503 uint32_t flags) 1504 { 1505 struct amdgpu_device *adev = ring->adev; 1506 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1507 1508 amdgpu_ring_write(ring, 1509 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); 1510 amdgpu_ring_write(ring, vmid); 1511 1512 amdgpu_ring_write(ring, 1513 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0)); 1514 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1515 amdgpu_ring_write(ring, 1516 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0)); 1517 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1518 amdgpu_ring_write(ring, 1519 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0)); 1520 amdgpu_ring_write(ring, ib->length_dw); 1521 } 1522 1523 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, 1524 uint32_t reg, uint32_t val, 1525 uint32_t mask) 1526 { 1527 struct amdgpu_device *adev = ring->adev; 1528 1529 amdgpu_ring_write(ring, 1530 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1531 amdgpu_ring_write(ring, reg << 2); 1532 amdgpu_ring_write(ring, 1533 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1534 amdgpu_ring_write(ring, val); 1535 amdgpu_ring_write(ring, 1536 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0)); 1537 amdgpu_ring_write(ring, mask); 1538 amdgpu_ring_write(ring, 1539 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1540 amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1); 1541 } 1542 1543 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, 1544 unsigned vmid, uint64_t pd_addr) 1545 { 1546 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1547 uint32_t data0, data1, mask; 1548 1549 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1550 1551 /* wait for register write */ 1552 data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2; 1553 data1 = lower_32_bits(pd_addr); 1554 mask = 0xffffffff; 1555 vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask); 1556 } 1557 1558 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, 1559 uint32_t reg, uint32_t val) 1560 { 1561 struct amdgpu_device *adev = ring->adev; 1562 1563 amdgpu_ring_write(ring, 1564 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0)); 1565 amdgpu_ring_write(ring, reg << 2); 1566 amdgpu_ring_write(ring, 1567 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0)); 1568 amdgpu_ring_write(ring, val); 1569 amdgpu_ring_write(ring, 1570 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0)); 1571 amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1); 1572 } 1573 1574 /** 1575 * vcn_v1_0_enc_ring_get_rptr - get enc read pointer 1576 * 1577 * @ring: amdgpu_ring pointer 1578 * 1579 * Returns the current hardware enc read pointer 1580 */ 1581 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring) 1582 { 1583 struct amdgpu_device *adev = ring->adev; 1584 1585 if (ring == &adev->vcn.inst->ring_enc[0]) 1586 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); 1587 else 1588 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); 1589 } 1590 1591 /** 1592 * vcn_v1_0_enc_ring_get_wptr - get enc write pointer 1593 * 1594 * @ring: amdgpu_ring pointer 1595 * 1596 * Returns the current hardware enc write pointer 1597 */ 1598 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring) 1599 { 1600 struct amdgpu_device *adev = ring->adev; 1601 1602 if (ring == &adev->vcn.inst->ring_enc[0]) 1603 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); 1604 else 1605 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); 1606 } 1607 1608 /** 1609 * vcn_v1_0_enc_ring_set_wptr - set enc write pointer 1610 * 1611 * @ring: amdgpu_ring pointer 1612 * 1613 * Commits the enc write pointer to the hardware 1614 */ 1615 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring) 1616 { 1617 struct amdgpu_device *adev = ring->adev; 1618 1619 if (ring == &adev->vcn.inst->ring_enc[0]) 1620 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, 1621 lower_32_bits(ring->wptr)); 1622 else 1623 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, 1624 lower_32_bits(ring->wptr)); 1625 } 1626 1627 /** 1628 * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command 1629 * 1630 * @ring: amdgpu_ring pointer 1631 * @fence: fence to emit 1632 * 1633 * Write enc a fence and a trap command to the ring. 1634 */ 1635 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 1636 u64 seq, unsigned flags) 1637 { 1638 WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 1639 1640 amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE); 1641 amdgpu_ring_write(ring, addr); 1642 amdgpu_ring_write(ring, upper_32_bits(addr)); 1643 amdgpu_ring_write(ring, seq); 1644 amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP); 1645 } 1646 1647 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring) 1648 { 1649 amdgpu_ring_write(ring, VCN_ENC_CMD_END); 1650 } 1651 1652 /** 1653 * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer 1654 * 1655 * @ring: amdgpu_ring pointer 1656 * @ib: indirect buffer to execute 1657 * 1658 * Write enc ring commands to execute the indirect buffer 1659 */ 1660 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring, 1661 struct amdgpu_job *job, 1662 struct amdgpu_ib *ib, 1663 uint32_t flags) 1664 { 1665 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 1666 1667 amdgpu_ring_write(ring, VCN_ENC_CMD_IB); 1668 amdgpu_ring_write(ring, vmid); 1669 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); 1670 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 1671 amdgpu_ring_write(ring, ib->length_dw); 1672 } 1673 1674 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring, 1675 uint32_t reg, uint32_t val, 1676 uint32_t mask) 1677 { 1678 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT); 1679 amdgpu_ring_write(ring, reg << 2); 1680 amdgpu_ring_write(ring, mask); 1681 amdgpu_ring_write(ring, val); 1682 } 1683 1684 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring, 1685 unsigned int vmid, uint64_t pd_addr) 1686 { 1687 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub]; 1688 1689 pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 1690 1691 /* wait for reg writes */ 1692 vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2, 1693 lower_32_bits(pd_addr), 0xffffffff); 1694 } 1695 1696 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring, 1697 uint32_t reg, uint32_t val) 1698 { 1699 amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE); 1700 amdgpu_ring_write(ring, reg << 2); 1701 amdgpu_ring_write(ring, val); 1702 } 1703 1704 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev, 1705 struct amdgpu_irq_src *source, 1706 unsigned type, 1707 enum amdgpu_interrupt_state state) 1708 { 1709 return 0; 1710 } 1711 1712 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev, 1713 struct amdgpu_irq_src *source, 1714 struct amdgpu_iv_entry *entry) 1715 { 1716 DRM_DEBUG("IH: VCN TRAP\n"); 1717 1718 switch (entry->src_id) { 1719 case 124: 1720 amdgpu_fence_process(&adev->vcn.inst->ring_dec); 1721 break; 1722 case 119: 1723 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]); 1724 break; 1725 case 120: 1726 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]); 1727 break; 1728 default: 1729 DRM_ERROR("Unhandled interrupt: %d %d\n", 1730 entry->src_id, entry->src_data[0]); 1731 break; 1732 } 1733 1734 return 0; 1735 } 1736 1737 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 1738 { 1739 struct amdgpu_device *adev = ring->adev; 1740 int i; 1741 1742 WARN_ON(ring->wptr % 2 || count % 2); 1743 1744 for (i = 0; i < count / 2; i++) { 1745 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0)); 1746 amdgpu_ring_write(ring, 0); 1747 } 1748 } 1749 1750 static int vcn_v1_0_set_powergating_state(void *handle, 1751 enum amd_powergating_state state) 1752 { 1753 /* This doesn't actually powergate the VCN block. 1754 * That's done in the dpm code via the SMC. This 1755 * just re-inits the block as necessary. The actual 1756 * gating still happens in the dpm code. We should 1757 * revisit this when there is a cleaner line between 1758 * the smc and the hw blocks 1759 */ 1760 int ret; 1761 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1762 1763 if(state == adev->vcn.cur_state) 1764 return 0; 1765 1766 if (state == AMD_PG_STATE_GATE) 1767 ret = vcn_v1_0_stop(adev); 1768 else 1769 ret = vcn_v1_0_start(adev); 1770 1771 if(!ret) 1772 adev->vcn.cur_state = state; 1773 return ret; 1774 } 1775 1776 static void vcn_v1_0_idle_work_handler(struct work_struct *work) 1777 { 1778 struct amdgpu_device *adev = 1779 container_of(work, struct amdgpu_device, vcn.idle_work.work); 1780 unsigned int fences = 0, i; 1781 1782 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1783 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1784 1785 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1786 struct dpg_pause_state new_state; 1787 1788 if (fences) 1789 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1790 else 1791 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1792 1793 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1794 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1795 else 1796 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1797 1798 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1799 } 1800 1801 fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec); 1802 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec); 1803 1804 if (fences == 0) { 1805 amdgpu_gfx_off_ctrl(adev, true); 1806 if (adev->pm.dpm_enabled) 1807 amdgpu_dpm_enable_uvd(adev, false); 1808 else 1809 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1810 AMD_PG_STATE_GATE); 1811 } else { 1812 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT); 1813 } 1814 } 1815 1816 void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring) 1817 { 1818 struct amdgpu_device *adev = ring->adev; 1819 bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work); 1820 1821 if (set_clocks) { 1822 amdgpu_gfx_off_ctrl(adev, false); 1823 if (adev->pm.dpm_enabled) 1824 amdgpu_dpm_enable_uvd(adev, true); 1825 else 1826 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN, 1827 AMD_PG_STATE_UNGATE); 1828 } 1829 1830 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) { 1831 struct dpg_pause_state new_state; 1832 unsigned int fences = 0, i; 1833 1834 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1835 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]); 1836 1837 if (fences) 1838 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1839 else 1840 new_state.fw_based = VCN_DPG_STATE__UNPAUSE; 1841 1842 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec)) 1843 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1844 else 1845 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; 1846 1847 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) 1848 new_state.fw_based = VCN_DPG_STATE__PAUSE; 1849 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG) 1850 new_state.jpeg = VCN_DPG_STATE__PAUSE; 1851 1852 adev->vcn.pause_dpg_mode(adev, 0, &new_state); 1853 } 1854 } 1855 1856 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { 1857 .name = "vcn_v1_0", 1858 .early_init = vcn_v1_0_early_init, 1859 .late_init = NULL, 1860 .sw_init = vcn_v1_0_sw_init, 1861 .sw_fini = vcn_v1_0_sw_fini, 1862 .hw_init = vcn_v1_0_hw_init, 1863 .hw_fini = vcn_v1_0_hw_fini, 1864 .suspend = vcn_v1_0_suspend, 1865 .resume = vcn_v1_0_resume, 1866 .is_idle = vcn_v1_0_is_idle, 1867 .wait_for_idle = vcn_v1_0_wait_for_idle, 1868 .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */, 1869 .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */, 1870 .soft_reset = NULL /* vcn_v1_0_soft_reset */, 1871 .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, 1872 .set_clockgating_state = vcn_v1_0_set_clockgating_state, 1873 .set_powergating_state = vcn_v1_0_set_powergating_state, 1874 }; 1875 1876 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { 1877 .type = AMDGPU_RING_TYPE_VCN_DEC, 1878 .align_mask = 0xf, 1879 .support_64bit_ptrs = false, 1880 .no_user_fence = true, 1881 .vmhub = AMDGPU_MMHUB_0, 1882 .get_rptr = vcn_v1_0_dec_ring_get_rptr, 1883 .get_wptr = vcn_v1_0_dec_ring_get_wptr, 1884 .set_wptr = vcn_v1_0_dec_ring_set_wptr, 1885 .emit_frame_size = 1886 6 + 6 + /* hdp invalidate / flush */ 1887 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + 1888 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 1889 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */ 1890 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */ 1891 6, 1892 .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */ 1893 .emit_ib = vcn_v1_0_dec_ring_emit_ib, 1894 .emit_fence = vcn_v1_0_dec_ring_emit_fence, 1895 .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush, 1896 .test_ring = amdgpu_vcn_dec_ring_test_ring, 1897 .test_ib = amdgpu_vcn_dec_ring_test_ib, 1898 .insert_nop = vcn_v1_0_dec_ring_insert_nop, 1899 .insert_start = vcn_v1_0_dec_ring_insert_start, 1900 .insert_end = vcn_v1_0_dec_ring_insert_end, 1901 .pad_ib = amdgpu_ring_generic_pad_ib, 1902 .begin_use = vcn_v1_0_ring_begin_use, 1903 .end_use = amdgpu_vcn_ring_end_use, 1904 .emit_wreg = vcn_v1_0_dec_ring_emit_wreg, 1905 .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait, 1906 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1907 }; 1908 1909 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { 1910 .type = AMDGPU_RING_TYPE_VCN_ENC, 1911 .align_mask = 0x3f, 1912 .nop = VCN_ENC_CMD_NO_OP, 1913 .support_64bit_ptrs = false, 1914 .no_user_fence = true, 1915 .vmhub = AMDGPU_MMHUB_0, 1916 .get_rptr = vcn_v1_0_enc_ring_get_rptr, 1917 .get_wptr = vcn_v1_0_enc_ring_get_wptr, 1918 .set_wptr = vcn_v1_0_enc_ring_set_wptr, 1919 .emit_frame_size = 1920 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + 1921 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + 1922 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */ 1923 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */ 1924 1, /* vcn_v1_0_enc_ring_insert_end */ 1925 .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */ 1926 .emit_ib = vcn_v1_0_enc_ring_emit_ib, 1927 .emit_fence = vcn_v1_0_enc_ring_emit_fence, 1928 .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush, 1929 .test_ring = amdgpu_vcn_enc_ring_test_ring, 1930 .test_ib = amdgpu_vcn_enc_ring_test_ib, 1931 .insert_nop = amdgpu_ring_insert_nop, 1932 .insert_end = vcn_v1_0_enc_ring_insert_end, 1933 .pad_ib = amdgpu_ring_generic_pad_ib, 1934 .begin_use = vcn_v1_0_ring_begin_use, 1935 .end_use = amdgpu_vcn_ring_end_use, 1936 .emit_wreg = vcn_v1_0_enc_ring_emit_wreg, 1937 .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait, 1938 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper, 1939 }; 1940 1941 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev) 1942 { 1943 adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs; 1944 DRM_INFO("VCN decode is enabled in VM mode\n"); 1945 } 1946 1947 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev) 1948 { 1949 int i; 1950 1951 for (i = 0; i < adev->vcn.num_enc_rings; ++i) 1952 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs; 1953 1954 DRM_INFO("VCN encode is enabled in VM mode\n"); 1955 } 1956 1957 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = { 1958 .set = vcn_v1_0_set_interrupt_state, 1959 .process = vcn_v1_0_process_interrupt, 1960 }; 1961 1962 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev) 1963 { 1964 adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2; 1965 adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs; 1966 } 1967 1968 const struct amdgpu_ip_block_version vcn_v1_0_ip_block = 1969 { 1970 .type = AMD_IP_BLOCK_TYPE_VCN, 1971 .major = 1, 1972 .minor = 0, 1973 .rev = 0, 1974 .funcs = &vcn_v1_0_ip_funcs, 1975 }; 1976
Indexes created Sat Sep 20 22:09:52 GMT 2025