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Searched refs:UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK (Results 1 - 13 of 13) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`810 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \| 992 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \| 1047 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \|`
amdgpu_uvd_v7_0.c	`877 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \| 992 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \|`
amdgpu_vcn_v2_0.c	`781 tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \| 909 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \|`
amdgpu_vcn_v2_5.c	`789 tmp = (0x8 \| UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \| 936 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \|`
amdgpu_uvd_v6_0.c	`747 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK \|`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`350 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L`
uvd_4_2_sh_mask.h	`353 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100`
uvd_5_0_sh_mask.h	`385 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100`
uvd_6_0_sh_mask.h	`387 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100`
uvd_7_0_sh_mask.h	`522 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1044 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L`
vcn_2_0_0_sh_mask.h	`2415 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L`
vcn_2_5_sh_mask.h	`3366 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L`

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