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Searched refs:UVD_MPC_SET_MUXA0__VARA_1__SHIFT (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`827 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) \| 1010 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) \|`
amdgpu_vcn_v2_0.c	`798 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) \| 922 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) \|`
amdgpu_vcn_v2_5.c	`806 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) \| 949 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) \|`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`501 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x00000006`
uvd_4_2_sh_mask.h	`486 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6`
uvd_5_0_sh_mask.h	`518 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6`
uvd_6_0_sh_mask.h	`520 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6`
uvd_7_0_sh_mask.h	`601 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1108 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6`
vcn_2_0_0_sh_mask.h	`2614 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6`
vcn_2_5_sh_mask.h	`2849 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6`

Completed in 53 milliseconds