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Searched refs:UVD_MPC_SET_MUXA0__VARA_2__SHIFT (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`828 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) \| 1011 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) \|`
amdgpu_vcn_v2_0.c	`799 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) \| 923 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) \|`
amdgpu_vcn_v2_5.c	`807 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) \| 950 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) \|`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`503 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0x0000000c`
uvd_4_2_sh_mask.h	`488 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc`
uvd_5_0_sh_mask.h	`520 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc`
uvd_6_0_sh_mask.h	`522 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc`
uvd_7_0_sh_mask.h	`602 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1109 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc`
vcn_2_0_0_sh_mask.h	`2615 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc`
vcn_2_5_sh_mask.h	`2850 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc`

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