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Searched refs:UVD_MPC_SET_MUXA0__VARA_4__SHIFT (Results 1 - 11 of 11) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v1_0.c	`830 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT))); 1013 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);`
amdgpu_vcn_v2_0.c	`801 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 925 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));`
amdgpu_vcn_v2_5.c	`809 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect); 952 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/uvd/
uvd_4_0_sh_mask.h	`507 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x00000018`
uvd_4_2_sh_mask.h	`492 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18`
uvd_5_0_sh_mask.h	`524 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18`
uvd_6_0_sh_mask.h	`526 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18`
uvd_7_0_sh_mask.h	`604 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18`
/src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/vcn/
vcn_1_0_sh_mask.h	`1111 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18`
vcn_2_0_0_sh_mask.h	`2617 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18`
vcn_2_5_sh_mask.h	`2852 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18`

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